openxiangshan / xiangshan

Open-source high-performance RISC-V processor

XiangShan

XiangShan (香山) is an open-source high-performance RISC-V processor project.

中文说明在此。

Copyright 2020-2022 by Institute of Computing Technology, Chinese Academy of Sciences.

Copyright 2020-2022 by Peng Cheng Laboratory.

Docs and slides

XiangShan-doc is our official documentation repository. It contains design spec., technical slides, tutorial and more.

• Micro-architecture documentation of XiangShan has been published. Please check out https://xiangshan-doc.readthedocs.io

Publications

MICRO 2022: Towards Developing High Performance RISC-V Processors Using Agile Methodology

Our paper introduces XiangShan and the practice of agile development methodology on high performance RISC-V processors. It covers some representative tools we have developed and used to accelerate the chip development process, including design, functional verification, debugging, performance validation, etc. This paper is awarded all three available badges for artifact evaluation (Available, Functional, and Reproduced).

Paper PDF | IEEE Xplore | BibTeX | Presentation Slides | Presentation Video

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Architecture

The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) on the yanqihu branch, which has been developed since June 2020.

The second stable micro-architecture of XiangShan is called Nanhu (南湖) on the nanhu branch.

The current version of XiangShan, also known as Kunminghu (昆明湖), is still under development on the master branch.

The micro-architecture overview of Nanhu (南湖) is shown below.

Sub-directories Overview

Some of the key directories are shown below.

.
├── src
│   └── main/scala         # design files
│       ├── device         # virtual device for simulation
│       ├── system         # SoC wrapper
│       ├── top            # top module
│       ├── utils          # utilization code
│       └── xiangshan      # main design code
│           └── transforms # some useful firrtl transforms
├── scripts                # scripts for agile development
├── fudian                 # floating unit submodule of XiangShan
├── huancun                # L2/L3 cache submodule of XiangShan
├── difftest               # difftest co-simulation framework
└── ready-to-run           # pre-built simulation images

IDE Support

bsp

make bsp

IDEA

make idea

Generate Verilog

• Run make verilog to generate verilog code. The output file is build/XSTop.v.
• Refer to Makefile for more information.

Run Programs by Simulation

Prepare environment

• Set environment variable NEMU_HOME to the absolute path of the NEMU project.
• Set environment variable NOOP_HOME to the absolute path of the XiangShan project.
• Set environment variable AM_HOME to the absolute path of the AM project.
• Install mill. Refer to the Manual section in this guide.
• Clone this project and run make init to initialize submodules.

Run with simulator

• Install Verilator, the open-source Verilog simulator.
• Run make emu to build the C++ simulator ./build/emu with Verilator.
• Refer to ./build/emu --help for run-time arguments of the simulator.
• Refer to Makefile and verilator.mk for more information.

Example:

make emu CONFIG=MinimalConfig EMU_THREADS=2 -j10
./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so

Troubleshooting Guide

Troubleshooting Guide

xiangshan's Issues

ready-to-run/riscv64-nemu-interpreter-so cannot be loaded

环境
ubuntu 18.04

输出
$ ./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so

Emu compiled at Jul 20 2021, 12:03:41
The image is ./ready-to-run/coremark-2-iteration.bin
Using simulated 8192MB RAM
[warning] sdcard img not found
Using ./ready-to-run/riscv64-nemu-interpreter-so for difftest
emu: /path/to/XiangShan/src/test/csrc/difftest/nemuproxy.cpp:50: NemuProxy::NemuProxy(int): Assertion `handle' failed.
[1] 122576 abort (core dumped) ./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff

检查编译结果，该文件存在
ls -al /path/to/XiangShan/ready-to-run/riscv64-nemu-interpreter-so
-rwxrwxr-x 1 {user} {user} 2076568 Jul 19 14:19 /path/to/XiangShan/ready-to-run/riscv64-nemu-interpreter-so

请教关于bpu中if3_prevHalfInstr的信号类型问题

我对于bpu中的if3_prevHalfInstr信号有个疑问。

在代码中if3_prevHalfInstr定义为reg，但是我觉得这个信号应该是wire？
if3_prevHalfInstr的赋值由从if4传过来的信号prevHalfInstrReq控制。（prevHalfInstrReq再控制信号if3_pendingPrevHalfInstr）
when (if3_prevHalfFlush) {
if3_prevHalfInstr.valid := false.B
}.elsewhen (hasPrevHalfInstrReq) {
if3_prevHalfInstr.valid := true.B
}.elsewhen (if3_prevHalfConsumed) {
if3_prevHalfInstr.valid := false.B
}
when (hasPrevHalfInstrReq) {
if3_prevHalfInstr.bits := prevHalfInstrReq.bits
}
然后if3_prevHalfInstr再产生if3_prevHalfInstrMet信号。
val if3_prevHalfInstrMet = if3_pendingPrevHalfInstr && if3_prevHalfInstr.bits.npc === if3_pc && if3_valid
这里就产生问题了。
假设流水线指令如下
if1 if2 if3 if4
inst4 inst3 inst2 inst1
假设在if4的指令if4_pc(inst1)满足saveHalfRVI条件，则此时inst1相关的信号赋给prevHalfInstrReq，prevHalfInstrReq是wire，
prevHalfInstrReq.bits.npc := snpc(if4_pc)，如果预测正确的化，snpc(if4_pc)应该就是if3_pc（inst2）。
prevHalfInstrReq又被赋给if3_prevHalfInstr。
但是因为if3_prevHalfInstr是reg所以要延一个周期，一个周期后if3_pc已经变成inst3，而不是inst2了，真正的inst2已经跑到if4了。
这样 if3_prevHalfInstr.bits.npc === if3_pc这个等式其实就有问题了，此时if3_prevHalfInstr.bits.npc其实应该要等于if4_pc才是正确的。
但是如果if3_prevHalfInstr是wire，这个等式就是对的了。
请看一下，谢谢

ExuIO相关的架构需要更新

ExuIO相关的架构需要更新: 目前所有的Exu均使用相同的ExuIO，无法为不同的功能单元提供不同的对外接口（如：Lsu对主存的访问）。

Atomic should not be handled by LSU

XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala

Line 125 in ab2d190

val atomicsUnit = Module(new AtomicsUnit)

Here is what we didn't in RocketChip
https://github.com/chipsalliance/rocket-chip/blob/86a2f2cca699f149bcc082ef2828654a0a4e3f4b/src/main/scala/rocket/DCache.scala#L558-L573

Why this is not good?

Atomic should be close to memory hierarchy to avoid live-lock, XiangShan implement this kind of Atomic is a bad design, which may introduce additional latency to atomic instruction: Xiangshan need acquire block from memory hierarchy, this will pollute L1D$, and may probe other cores(additional latency from coherence management).
If different cores try to lock a same address with atomic instructions, this will introduce live locks. which is dangerous for a bus interconnection!

How to resolve it?

TileLink directly support this via its spec. So bypass to bus interconnect will be better.
I think this is something need to be managed by system cache or broadcast(coherence manager), since they are close to memory, but only one thing you need to handle additionally is periphery devices, since they are not handled by coherence.
https://github.com/chipsalliance/rocket-chip/blob/86a2f2cca699f149bcc082ef2828654a0a4e3f4b/src/main/scala/subsystem/PeripheryBus.scala#L51-L58
You need a additional bus device to take over this.

master分支中difftest模块编译过程中跟NOOP_HOME、NEMU_HOME两个环境变量最好解耦开。NOOP_HOME可以通过相对目录关系解决。而NEMU_HOME是不是不是必须的？

master分支中difftest模块编译过程中跟NOOP_HOME、NEMU_HOME两个环境变量最好解耦开。NOOP_HOME可以通过相对目录关系解决。而NEMU_HOME是不是不是必须的？

class ExuWbArbiter中特意将ctrl与data分开使用两个Arbiter，这个基于什么考虑呢？ 是为了避免位宽大导致延时比较大么？

class ExuWbArbiter(n: Int)(implicit p: Parameters) extends XSModule {
val io = IO(new Bundle() {
val in = Vec(n, Flipped(DecoupledIO(new ExuOutput)))
val out = DecoupledIO(new ExuOutput)
})

class ExuCtrl extends Bundle{
val uop = new MicroOp
val fflags = UInt(5.W)
val redirectValid = Bool()
val redirect = new Redirect
val debug = new DebugBundle
}
val ctrl_arb = Module(new Arbiter(new ExuCtrl, n))
val data_arb = Module(new Arbiter(UInt((XLEN+1).W), n))

yanqihu分支的build.sc文件引用了不存在的文件

build.sc里面引用部分：
import os.Path
import mill._
import mill.modules.Util
import $ivy.com.lihaoyi::mill-contrib-buildinfo:$MILL_VERSION
import $ivy.com.lihaoyi::mill-contrib-bsp:$MILL_VERSION
import mill.contrib.buildinfo.BuildInfo
import scalalib._
import coursier.maven.MavenRepository

这里面contrib-bsp已经不存在了。需要修改，否则无法mill构建

how to apply SimTop.v in Vivado

load source file /root/riscv_cpu/XiangShan/build/SimTop.v
/root/riscv_cpu/XiangShan/build/plusarg_reader.v
or
/root/riscv_cpu/XiangShan/build/XSTop.v
/root/riscv_cpu/XiangShan/build/plusarg_reader.v

make Schematic failed
[Synth 8-439] module 'plusarg_reader' not found ["/root/riscv_cpu/XiangShan/build/SimTop.v":622]
[Synth 8-6156] failed synthesizing module 'TLMonitor' ["/root/riscv_cpu/XiangShan/build/SimTop.v":35]
[Vivado_Tcl 4-5] Elaboration failed - please see the console for details

how to to use it correctly?

Use GenVerilogMemBehaviorModelAnno to replace vlsi_mem_gen

This feature will be introduced since FIRRTL 1.5
See example:
https://github.com/sequencer/chipsalliance-playground/blob/6272ef59bb1481b8c1362d70468ac546505f2303/sanitytests/rocketchip/src/TestHarness.scala#L21-L38

master 分支在加入difftest子文件夹代码后，build.sbt文件希望添加对应的依赖，这样sbt构建环境简单修改Makefile就可支持了，毕竟有些需要经过代理的网络mill工具配置还是比较麻烦的，谢谢！

下面是修改后可以支持sbt构建的，可以参考，谢谢！
xiangshan_code_root_folder# git diff build.sbt
diff --git a/build.sbt b/build.sbt
index f6a092c..1421e3c
--- a/build.sbt
+++ b/build.sbt
@@ -45,9 +45,12 @@ lazy val block-inclusive-cache = (project in file("block-inclusivecache-sifive
)
.dependsOn(rocket-chip)

+lazy val difftest = (project in file("difftest"))

• .settings(commonSettings, chiselSettings)

lazy val chiseltest = (project in file("chiseltest"))
.settings(commonSettings, chiselSettings)

lazy val xiangshan = (Project("XiangShan", base = file(".")))
.settings(commonSettings, chiselSettings)

• .dependsOn(rocket-chip, block-inclusive-cache, chiseltest)
  \ No newline at end of file

• .dependsOn(rocket-chip, block-inclusive-cache, chiseltest, difftest)
  \ No newline at end of file

idea java.lang.StackOverflowError

When Idea in debug mode it will StackOverflowError
There are recursive happend, how do i modify those code

///
Exception in thread "main" java.lang.StackOverflowError
at firrtl.transforms.ConstantPropagation.regConstant$1(ConstantPropagation.scala:717)
at firrtl.transforms.ConstantPropagation.$anonfun$constPropModule$14(ConstantPropagation.scala:714)
at scala.collection.mutable.HashMap.getOrElseUpdate(HashMap.scala:86)
at firrtl.transforms.ConstantPropagation.regConstant$1(ConstantPropagation.scala:714)
at firrtl.transforms.ConstantPropagation.regConstant$1(ConstantPropagation.scala:717)
at firrtl.transforms.ConstantPropagation.$anonfun$constPropModule$14(ConstantPropagation.scala:714)
at scala.collection.mutable.HashMap.getOrElseUpdate(HashMap.scala:86)
at firrtl.transforms.ConstantPropagation.regConstant$1(ConstantPropagation.scala:714)
at firrtl.transforms.ConstantPropagation.regConstant$1(ConstantPropagation.scala:717)
at firrtl.transforms.ConstantPropagation.$anonfun$constPropModule$14(ConstantPropagation.scala:714)
at scala.collection.mutable.HashMap.getOrElseUpdate(HashMap.scala:86)
at firrtl.transforms.ConstantPropagation.regConstant$1(ConstantPropagation.scala:714)
at firrtl.transforms.ConstantPropagation.regConstant$1(ConstantPropagation.scala:717)
at firrtl.transforms.ConstantPropagation.$anonfun$constPropModule$14(ConstantPropagation.scala:714)
at scala.collection.mutable.HashMap.getOrElseUpdate(HashMap.scala:86)
at firrtl.transforms.ConstantPropagation.regConstant$1(ConstantPropagation.scala:714)
at firrtl.transforms.ConstantPropagation.regConstant$1(ConstantPropagation.scala:717)
at firrtl.transforms.ConstantPropagation.$anonfun$constPropModule$14(ConstantPropagation.scala:714)
at scala.collection.mutable.HashMap.getOrElseUpdate(HashMap.scala:86)
at firrtl.transforms.ConstantPropagation.regConstant$1(ConstantPropagation.scala:714)
at firrtl.transforms.ConstantPropagation.regConstant$1(ConstantPropagation.scala:717)
at firrtl.transforms.ConstantPropagation.$anonfun$constPropModule$14(ConstantPropagation.scala:714)
at scala.collection.mutable.HashMap.getOrElseUpdate(HashMap.scala:86)

build.sc中的依赖是如何得到的

object XiangShan extends CommonModule with SbtModule {
override def millSourcePath = millOuterCtx.millSourcePath

override def forkArgs = Seq("-Xmx10G")

override def ivyDeps = super.ivyDeps() ++ chisel
override def moduleDeps = super.moduleDeps ++ Seq(
rocket-chip,
block-inclusivecache-sifive,
chiseltest
)

object test extends Tests {
override def forkArgs = Seq("-Xmx10G")
override def ivyDeps = super.ivyDeps() ++ Agg(
ivy"org.scalatest::scalatest:3.2.0"
)

def testFrameworks = Seq(
  "org.scalatest.tools.Framework"
)

def testOnly(args: String*) = T.command {
  super.runMain("org.scalatest.tools.Runner", args: _*)
}

}

}

在 build.sc 里面xiangshan 依赖 是上面这么写，然后makefile里面 调用的是 XiangShan.test.runMain， 这个 是个 Xiangshan 类的类成员 test的 函数，然而 依赖放在 xiangshan这个类里面的， 我想请教一下 类的 类成员是如何从类得到依赖的， 还是 利用了scala 有什么特殊特性

我是Java程序员 如何做贡献

希望对RISC-V在**的生态发展做一点点贡献

要不要建一个微信群 或者 bbs

请问你们的验证足够吗？想过UVM吗？

我想起来开发一个UVM testbench 送给香山，你们觉得用C和一些Scala测试足够吗？其他团队人会使用UVM吗？我想帮助验证过程

make verilog error

你好，
我正在编译象山，但出现此错误（错误在屏幕截图中)
关联：https://imgur.com/V8U7Qsl

编译verilog CONFIG=MinimalConfig 出错

[deprecated] ListBuffer.scala:153 (4 calls): do_toBools is deprecated: "Use asBools instead"
[deprecated] ListBuffer.scala:164 (4 calls): do_toBools is deprecated: "Use asBools instead"
[warn] There were 2 deprecated function(s) used. These may stop compiling in a future release - you are encouraged to fix these issues.
[warn] Line numbers for deprecations reported by Chisel may be inaccurate; enable scalac compiler deprecation warnings via either of the following methods:
[warn] In the sbt interactive console, enter:
[warn] set scalacOptions in ThisBuild ++= Seq("-unchecked", "-deprecation")
[warn] or, in your build.sbt, add the line:
[warn] scalacOptions := Seq("-unchecked", "-deprecation")
Done elaborating.
xiangshan.backend.MemBlock@45e34a32
./scripts/vlsi_mem_gen build/XSTop.v.conf --tsmc28 --output_file build/tsmc28_sram.v > build/tsmc28_sram.v.conf
./scripts/vlsi_mem_gen build/XSTop.v.conf --output_file build/sim_sram.v
# sed -i -e 's/(aw|ar|w|r|b)(|bits_)/_\1/g' build/XSTop.v
fatal: 您的当前分支 'master' 尚无任何提交
make: *** [Makefile:54：build/XSTop.v] 错误 128

请问这是什么情况呢？

中文文档链接失效

如题，英文跳转到中文的链接失效

关于 `src/test/csrc/main.cpp` 里面返回值的问题

目前 src/test/csrc/main.cpp 里面是这样返回的：

return !is_good_trap;

这样写的话 emu 返回值只能是 0 或 1, 返回 0 代表程序正常返回，仿真一切正常；返回 1 即表示程序异常返回，仿真中出现问题，但是我们不知道是什么异常。
这样带来的问题：

• 监控程序或其他外部程序无法从返回结果知道仿真过程中出现什么类型的错误
• emu 后带 -I 参数后即使仿真正确，返回值也是 1，这时候自动化测试脚本将会认为该仿真过程出现了错误，从而回退 10000 个周期继续仿真。虽然我们可以检查输出文件来判断这种带 -I 参数的仿真正常与否，但这不是一个优雅的做法。

个人建议做以下修改：

// emu.h:  
class Emulator {
 ......
endif
EmuArgs args;

enum {
 STATE_GOODTRAP = 0,
 STATE_BADTRAP = 1,
 STATE_ABORT = 2,
 STATE_LIMIT_EXCEEDED = 3,
 STATE_RUNNING = -1
 };

......

public:  
......
bool is_good_trap() { return trapCode == STATE_GOODTRAP; };
int trap_code() { return trapCode; }
};

// main.cpp:  
int main(int argc, const char** argv) {
......
int trapcode = emu->trap_code();
 ......
 return trapcode;
}

这样子我们就可以通过程序返回值来判断仿真的状态了，比如：

try:
            cmd( # TODO  )
        except sh.ErrorReturnCode_1 as e:
            # TODO
            pass
        except sh.ErrorReturnCode_2 as e:
            # TODO
            pass
        except sh.ErrorReturnCode_3 as e:
            # TODO
            pass

制作bbl.bin失败

我是按照Linux Kernel 的构建.md里面的方法想自己构建一个bbl.bin。
1、riscv-linux我是下的压缩包：riscv-linux-nanshan.zip。编译vmlinux，来看也编译出来了。
drwxr-sr-x 4 root nopasswdlogin 4096 7月 12 13:16 virt
-rwxr-xr-x 1 root nopasswdlogin 1401056 7月 12 13:16 vmlinux
-rw-r--r-- 1 root nopasswdlogin 112 7月 12 13:16 .vmlinux.cmd
-rw-r--r-- 1 root nopasswdlogin 4569448 7月 12 13:16 vmlinux.o

2、riscv-rootfs，里面的hello也编译了

3、riscv-pk这块编译错误：
root@zte-R5300-G4:/share/zhuxuanlong/XiangShan/riscv-pk/dts# rm platform.dtsi
root@zte-R5300-G4:/share/zhuxuanlong/XiangShan/riscv-pk/dts# ln -s noop.dtsi platform.dtsi
root@zte-R5300-G4:/share/zhuxuanlong/XiangShan/riscv-pk/dts# ls -al
总用量 28
drwxr-sr-x 2 root nopasswdlogin 4096 7月 12 13:20 .
drwxr-sr-x 11 root nopasswdlogin 4096 7月 1 15:09 ..
-rw-r--r-- 1 root nopasswdlogin 801 7月 1 15:09 nemu.dtsi
-rw-r--r-- 1 root nopasswdlogin 691 7月 1 15:09 noop.dtsi
lrwxrwxrwx 1 root nopasswdlogin 9 7月 12 13:20 platform.dtsi -> noop.dtsi
-rw-r--r-- 1 root nopasswdlogin 4012 7月 1 15:09 PXIe.dtsi
-rw-r--r-- 1 root nopasswdlogin 1249 7月 1 15:09 system.dts
-rw-r--r-- 1 root nopasswdlogin 2201 7月 1 15:09 zynq-standalone.dtsi

root@zte-R5300-G4:/share/zhuxuanlong/XiangShan/riscv-pk# make clean
rm -rf build
root@zte-R5300-G4:/share/zhuxuanlong/XiangShan/riscv-pk#
root@zte-R5300-G4:/share/zhuxuanlong/XiangShan/riscv-pk#
root@zte-R5300-G4:/share/zhuxuanlong/XiangShan/riscv-pk#
root@zte-R5300-G4:/share/zhuxuanlong/XiangShan/riscv-pk# make noop -j
RISCV_ROOTFS_HOME=/share/zhuxuanlong/XiangShan/riscv-rootfs make -C /share/zhuxuanlong/XiangShan/riscv-rootfs
mkdir -p build
mkdir -p build
dtc -O dtb -I dts -o build/system.dtb dts/system.dts
cd build && /share/zhuxuanlong/XiangShan/riscv-pk/configure --host=riscv64-unknown-elf --with-payload=/share/zhuxuanlong/XiangShan/riscv-linux-nanshan/riscv-linux-nanshan/vmlinux --with-arch=rv64imac --enable-logo
Error: dts/platform.dtsi:1.1-9 syntax error
FATAL ERROR: Unable to parse input tree
make[1]: 进入目录“/share/zhuxuanlong/XiangShan/riscv-rootfs”
make: *** [Makefile:60：build/system.dtb] 错误 1
make: *** 正在等待未完成的任务....
echo apps/hello
echo apps/stream
echo apps/busybox
echo apps/redis
apps/hello
echo apps/dwarf/md5
apps/stream
make -s -C apps/hello install
apps/busybox
make -s -C apps/stream install
apps/redis
make -s -C apps/busybox install
apps/dwarf/md5
make -s -C apps/redis install
make -s -C apps/dwarf/md5 install
echo apps/dwarf/sort
echo apps/dwarf/wordcount
make[2]: 进入目录“/share/zhuxuanlong/XiangShan/riscv-rootfs/apps/hello”
apps/dwarf/sort
make -s -C apps/dwarf/sort install
make[2]: 进入目录“/share/zhuxuanlong/XiangShan/riscv-rootfs/apps/stream”
apps/dwarf/wordcount

编译时间太久

[deprecated] ListBuffer.scala:153 (5 calls): do_toBools is deprecated: "Use asBools instead"
[deprecated] ListBuffer.scala:164 (5 calls): do_toBools is deprecated: "Use asBools instead"
[warn] There were 2 deprecated function(s) used. These may stop compiling in a future release - you are encouraged to fix these issues.
[warn] Line numbers for deprecations reported by Chisel may be inaccurate; enable scalac compiler deprecation warnings via either of the following methods:
[warn] In the sbt interactive console, enter:
[warn] set scalacOptions in ThisBuild ++= Seq("-unchecked", "-deprecation")
[warn] or, in your build.sbt, add the line:
[warn] scalacOptions := Seq("-unchecked", "-deprecation")
Done elaborating.
这个界面停留了很久，近1个小时， build/XStop.v 这个文件也没有生成出来，这个是什么情况呢

请教一个关于renametable的问题

renametable的io.flush来自roq的io.flushOut.valid信号，并在io.flushOut.valid的基础上延了一拍，这个时间roq已经被清空了，不应该再有指令提交，可是不知道为什么renametable的代码中，在io.flush时还有可能在io.archWritePorts有因为指令commit而产生的写入？
谢谢
when (io.flush) {
spec_table := arch_table
// spec table needs to be updated when flushPipe
for (w <- io.archWritePorts) {
when(w.wen){ spec_table(w.addr) := w.wdata }
}
}

%Error: build/SimTop.v:2487721:3: Cannot find file containing module: 'array_18_ext'

ubuntu 16.04
make emu
Sat, 17 Jul 2021 11:07:13 +0800
time -a -o ./build/time.log verilator --cc --exe --top-module SimTop +define+VERILATOR=1 +define+PRINTF_COND=1 +define+RANDOMIZE_REG_INIT +define+RANDOMIZE_MEM_INIT +define+RANDOMIZE_GARBAGE_ASSIGN +define+RANDOMIZE_DELAY=0 -Wno-STMTDLY -Wno-WIDTH -I/opt/home/llw/tmp/xiangshan/XiangShan/build --x-assign unique -O3 -CFLAGS "-std=c++11 -static -Wall -I/opt/home/llw/tmp/xiangshan/XiangShan/src/test/csrc/verilator -I/opt/home/llw/tmp/xiangshan/XiangShan/src/test/csrc/common -I/opt/home/llw/tmp/xiangshan/XiangShan/src/test/csrc/difftest -DVERILATOR -Wno-maybe-uninitialized -DNUM_CORES=1" -LDFLAGS "-lpthread -lSDL2 -ldl -lz" --assert --stats-vars --output-split 30000 --output-split-cfuncs 30000
-o /opt/home/llw/tmp/xiangshan/XiangShan/build/emu -Mdir build/emu-compile build/SimTop.v ./src/test/vsrc/common/difftest.v ./src/test/vsrc/common/ref.v ./src/test/vsrc/common/assert.v ./src/test/vsrc/common/ram.v /opt/home/llw/tmp/xiangshan/XiangShan/src/test/csrc/verilator/emu.cpp /opt/home/llw/tmp/xiangshan/XiangShan/src/test/csrc/verilator/main.cpp /opt/home/llw/tmp/xiangshan/XiangShan/src/test/csrc/verilator/snapshot.cpp /opt/home/llw/tmp/xiangshan/XiangShan/src/test/csrc/common/ram.cpp /opt/home/llw/tmp/xiangshan/XiangShan/src/test/csrc/common/uart.cpp /opt/home/llw/tmp/xiangshan/XiangShan/src/test/csrc/common/keyboard.cpp /opt/home/llw/tmp/xiangshan/XiangShan/src/test/csrc/common/vga.cpp /opt/home/llw/tmp/xiangshan/XiangShan/src/test/csrc/common/compress.cpp /opt/home/llw/tmp/xiangshan/XiangShan/src/test/csrc/common/device.cpp /opt/home/llw/tmp/xiangshan/XiangShan/src/test/csrc/common/flash.cpp /opt/home/llw/tmp/xiangshan/XiangShan/src/test/csrc/common/sdcard.cpp /opt/home/llw/tmp/xiangshan/XiangShan/src/test/csrc/common/common.cpp /opt/home/llw/tmp/xiangshan/XiangShan/src/test/csrc/common/axi4.cpp /opt/home/llw/tmp/xiangshan/XiangShan/src/test/csrc/difftest/interface.cpp /opt/home/llw/tmp/xiangshan/XiangShan/src/test/csrc/difftest/difftest.cpp /opt/home/llw/tmp/xiangshan/XiangShan/src/test/csrc/difftest/goldenmem.cpp /opt/home/llw/tmp/xiangshan/XiangShan/src/test/csrc/difftest/ref.cpp /opt/home/llw/tmp/xiangshan/XiangShan/src/test/csrc/difftest/nemuproxy.cpp
%Error: build/SimTop.v:2487721:3: Cannot find file containing module: 'array_18_ext'
2487721 | array_18_ext array_18_ext (
| ^~~~~~~~~~~~
... Looked in:
/opt/home/llw/tmp/xiangshan/XiangShan/build/array_18_ext
/opt/home/llw/tmp/xiangshan/XiangShan/build/array_18_ext.v
/opt/home/llw/tmp/xiangshan/XiangShan/build/array_18_ext.sv
array_18_ext
array_18_ext.v
array_18_ext.sv
build/emu-compile/array_18_ext
build/emu-compile/array_18_ext.v
build/emu-compile/array_18_ext.sv
%Error: build/SimTop.v:2487665:3: Cannot find file containing module: 'array_17_ext'
2487665 | array_17_ext array_17_ext (
| ^~~~~~~~~~~~
%Error: build/SimTop.v:2487167:3: Cannot find file containing module: 'array_8_ext'
2487167 | array_8_ext array_8_ext (
| ^~~~~~~~~~~
%Error: build/SimTop.v:2487008:3: Cannot find file containing module: 'array_7_ext'
2487008 | array_7_ext array_7_ext (
| ^~~~~~~~~~~
%Error: build/SimTop.v:2486903:3: Cannot find file containing module: 'array_6_ext'
2486903 | array_6_ext array_6_ext (
| ^~~~~~~~~~~
%Error: build/SimTop.v:2486798:3: Cannot find file containing module: 'array_5_ext'
2486798 | array_5_ext array_5_ext (
| ^~~~~~~~~~~
%Error: build/SimTop.v:2486693:3: Cannot find file containing module: 'array_4_ext'
2486693 | array_4_ext array_4_ext (
| ^~~~~~~~~~~
%Error: build/SimTop.v:2486588:3: Cannot find file containing module: 'array_3_ext'
2486588 | array_3_ext array_3_ext (
| ^~~~~~~~~~~
%Error: build/SimTop.v:2487627:3: Cannot find file containing module: 'array_16_ext'
2487627 | array_16_ext array_16_ext (
| ^~~~~~~~~~~~
%Error: build/SimTop.v:2487282:3: Cannot find file containing module: 'array_10_ext'
2487282 | array_10_ext array_10_ext (
| ^~~~~~~~~~~~
%Error: build/SimTop.v:2487248:3: Cannot find file containing module: 'array_9_ext'
2487248 | array_9_ext array_9_ext (
| ^~~~~~~~~~~
%Error: build/SimTop.v:2486483:3: Cannot find file containing module: 'array_2_ext'
2486483 | array_2_ext array_2_ext (
| ^~~~~~~~~~~
%Error: build/SimTop.v:2486399:3: Cannot find file containing module: 'array_1_ext'
2486399 | array_1_ext array_1_ext (
| ^~~~~~~~~~~
%Error: build/SimTop.v:2486337:3: Cannot find file containing module: 'array_0_ext'
2486337 | array_0_ext array_0_ext (
| ^~~~~~~~~~~
%Error: build/SimTop.v:2486164:3: Cannot find file containing module: 'array_ext'
2486164 | array_ext array_ext (
| ^~~~~~~~~
%Error: build/SimTop.v:2487834:3: Cannot find file containing module: 'array_21_ext'
2487834 | array_21_ext array_21_ext (
| ^~~~~~~~~~~~
%Error: build/SimTop.v:2487798:3: Cannot find file containing module: 'array_20_ext'
2487798 | array_20_ext array_20_ext (
| ^~~~~~~~~~~~
%Error: build/SimTop.v:2487762:3: Cannot find file containing module: 'array_19_ext'
2487762 | array_19_ext array_19_ext (
| ^~~~~~~~~~~~
%Error: build/SimTop.v:2487554:3: Cannot find file containing module: 'array_15_ext'
2487554 | array_15_ext array_15_ext (
| ^~~~~~~~~~~~
%Error: build/SimTop.v:2487461:3: Cannot find file containing module: 'array_14_ext'
2487461 | array_14_ext array_14_ext (
| ^~~~~~~~~~~~
%Error: build/SimTop.v:2487396:3: Cannot find file containing module: 'array_13_ext'
2487396 | array_13_ext array_13_ext (
| ^~~~~~~~~~~~
%Error: build/SimTop.v:2487340:3: Cannot find file containing module: 'array_12_ext'
2487340 | array_12_ext array_12_ext (
| ^~~~~~~~~~~~
%Error: build/SimTop.v:2487311:3: Cannot find file containing module: 'array_11_ext'
2487311 | array_11_ext array_11_ext (
| ^~~~~~~~~~~~
%Error: build/SimTop.v:2487961:3: Cannot find file containing module: 'array_24_ext'
2487961 | array_24_ext array_24_ext (
| ^~~~~~~~~~~~
%Error: build/SimTop.v:2487923:3: Cannot find file containing module: 'array_23_ext'
2487923 | array_23_ext array_23_ext (
| ^~~~~~~~~~~~
%Error: build/SimTop.v:2487867:3: Cannot find file containing module: 'array_22_ext'
2487867 | array_22_ext array_22_ext (
| ^~~~~~~~~~~~
%Error: build/SimTop.v:2488055:3: Cannot find file containing module: 'array_26_ext'
2488055 | array_26_ext array_26_ext (
| ^~~~~~~~~~~~
%Error: build/SimTop.v:2488017:3: Cannot find file containing module: 'array_25_ext'
2488017 | array_25_ext array_25_ext (
| ^~~~~~~~~~~~
%Error: Exiting due to 28 error(s)
verilator.mk:104: recipe for target 'build/emu-compile/VSimTop.mk' failed
make: *** [build/emu-compile/VSimTop.mk] Error 1

下载XiangShan子模块无法下载berkeley-softfloat-3

您好！
我的环境是公司内网，用的是我司的服务器，CPU是双路 Intel(R) Xeon(R) Silver 4114 CPU @ 2.20GHz，内存376G。下载XiangShan代码，make init命令提示已经全部下载完毕，但通过git submodule update --init --recursive 等手动命令提示无法下载berkeley-softfloat-3。我在网页上通过登录XiangShan代码仓库是可以直接打开此代码的。
root@zte-R5300-G4:/share/zhuxuanlong/XiangShan/XiangShan# make init
git submodule update --init
root@zte-R5300-G4:/share/zhuxuanlong/XiangShan/XiangShan#
root@zte-R5300-G4:/share/zhuxuanlong/XiangShan/XiangShan#
root@zte-R5300-G4:/share/zhuxuanlong/XiangShan/XiangShan#
root@zte-R5300-G4:/share/zhuxuanlong/XiangShan/XiangShan# git submodule update --init --recursive
正克隆到 'berkeley-softfloat-3'...
fatal: unable to connect to github.com:
github.com[0: 52.74.223.119]: errno=连接超时

fatal: 无法克隆 'git://github.com/ucb-bar/berkeley-softfloat-3.git' 到子模组路径 'berkeley-softfloat-3'
无法递归进子模组路径 'berkeley-hardfloat'

root@zte-R5300-G4:/share/zhuxuanlong/XiangShan/XiangShan# git remote -v
origin https://github.com/OpenXiangShan/XiangShan.git (fetch)
origin https://github.com/OpenXiangShan/XiangShan.git (push)

make emu error

Hi,

Thanks for this great open source CPU.

After I successfully make verilog. I tried make emu. But the error occurs, and the error info is as follows.
Thank your very much for any suggestion.

Error output

Connection:[DISPLAY_LOG_ENABLE] type:[func] source location:[SimTop] sink location:[AXI4RAM_1]
Connection:[logTimestamp] type:[func] source location:[SimTop] sink location:[AXI4RAM_1]
Connection:[XSPERF_CLEAN] type:[func] source location:[SimTop] sink location:[L2Prefetcher]
Connection:[XSPERF_DUMP] type:[func] source location:[SimTop] sink location:[L2Prefetcher]
[deprecated] ListBuffer.scala:153 (5 calls): do_toBools is deprecated: "Use asBools instead"
[deprecated] ListBuffer.scala:164 (5 calls): do_toBools is deprecated: "Use asBools instead"
[warn] There were 2 deprecated function(s) used. These may stop compiling in a future release - you are encouraged to fix these issues.
[warn] Line numbers for deprecations reported by Chisel may be inaccurate; enable scalac compiler deprecation warnings via either of the following methods:
[warn] In the sbt interactive console, enter:
[warn] set scalacOptions in ThisBuild ++= Seq("-unchecked", "-deprecation")
[warn] or, in your build.sbt, add the line:
[warn] scalacOptions := Seq("-unchecked", "-deprecation")
Done elaborating.
./scripts/vlsi_mem_gen build/SimTop.v.conf --output_file build/SimTop.v.sram.v
sed -i -e 's/$fatal/xs_assert(`LINE)/g' ./build/SimTop.v
Sat, 26 Jun 2021 17:38:50 +0800
time -a -o ./build/time.log verilator --cc --exe --top-module SimTop +define+VERILATOR=1 +define+PRINTF_COND=1 +define+RANDOMIZE_REG_INIT +define+RANDOMIZE_MEM_INIT +define+RANDOMIZE_GARBAGE_ASSIGN +define+RANDOMIZE_DELAY=0 -Wno-STMTDLY -Wno-WIDTH -I/home/username/riscv/open_xiangshan/XiangShan/build --x-assign unique -O3 -CFLAGS "-std=c++11 -static -Wall -I/home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/verilator -I/home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/common -I/home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/difftest -DVERILATOR -Wno-maybe-uninitialized" -LDFLAGS "-lpthread -lSDL2 -ldl -lz" --assert --stats-vars --output-split 30000 --output-split-cfuncs 30000
-o /home/username/riscv/open_xiangshan/XiangShan/build/emu -Mdir build/emu-compile build/SimTop.v ./src/test/vsrc/common/assert.v ./src/test/vsrc/common/difftest.v ./src/test/vsrc/common/ref.v ./src/test/vsrc/common/ram.v /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/verilator/emu.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/verilator/main.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/verilator/snapshot.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/common/compress.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/common/uart.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/common/ram.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/common/common.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/common/axi4.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/common/sdcard.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/common/vga.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/common/flash.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/common/keyboard.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/common/device.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/difftest/difftest.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/difftest/goldenmem.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/difftest/ref.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/difftest/nemuproxy.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/difftest/interface.cpp
Killed
%Error: Command Failed /usr/bin/verilator_bin --cc --exe --top-module SimTop +define+VERILATOR=1 +define+PRINTF_COND=1 +define+RANDOMIZE_REG_INIT +define+RANDOMIZE_MEM_INIT +define+RANDOMIZE_GARBAGE_ASSIGN +define+RANDOMIZE_DELAY=0 -Wno-STMTDLY -Wno-WIDTH -I/home/username/riscv/open_xiangshan/XiangShan/build --x-assign unique -O3 -CFLAGS -std=c++11\ -static\ -Wall\ -I/home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/verilator\ -I/home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/common\ -I/home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/difftest\ -DVERILATOR\ -Wno-maybe-uninitialized -LDFLAGS -lpthread\ -lSDL2\ -ldl\ -lz --assert --stats-vars --output-split 30000 --output-split-cfuncs 30000 -o /home/username/riscv/open_xiangshan/XiangShan/build/emu -Mdir build/emu-compile build/SimTop.v ./src/test/vsrc/common/assert.v ./src/test/vsrc/common/difftest.v ./src/test/vsrc/common/ref.v ./src/test/vsrc/common/ram.v /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/verilator/emu.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/verilator/main.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/verilator/snapshot.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/common/compress.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/common/uart.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/common/ram.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/common/common.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/common/axi4.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/common/sdcard.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/common/vga.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/common/flash.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/common/keyboard.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/common/device.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/difftest/difftest.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/difftest/goldenmem.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/difftest/ref.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/difftest/nemuproxy.cpp /home/username/riscv/open_xiangshan/XiangShan/src/test/csrc/difftest/interface.cpp
make: *** [verilator.mk:107: build/emu-compile/VSimTop.mk] Error 137

My environment:

$ java --version
openjdk 11.0.11 2021-04-20
OpenJDK Runtime Environment (build 11.0.11+9-Ubuntu-0ubuntu2.20.04)
OpenJDK 64-Bit Server VM (build 11.0.11+9-Ubuntu-0ubuntu2.20.04, mixed mode, sharing)

$ mill --version
Mill Build Tool version 0.9.6
Java version: 11.0.11, vendor: Ubuntu, runtime: /usr/lib/jvm/java-11-openjdk-amd64
Default locale: en, platform encoding: UTF-8
OS name: "Linux", version: 5.4.72-microsoft-standard-WSL2, arch: amd64

$ verilator --version
Verilator 4.028 2020-02-06 rev v4.026-92-g890cecc1

$gcc --version
gcc (Ubuntu 9.3.0-17ubuntu1~20.04) 9.3.0
Copyright (C) 2019 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

请问有没有啥群组方便交流学习的？

作为riscv刚入门的同学，我们学校也没有像你们这样专业统一的团队，最近在阅读rocketchip dcache部分源码，没啥注释遇到问题也只能自己琢磨，想必各位应该对伯克利开源的项目理解的很透彻，因此想向各位请教学习。

make error : not found: value hardfloat

$ make verilog
mkdir -p build
mill XiangShan.runMain top.TopMain -td build --config DefaultConfig --full-stacktrace --output-file XSTop.v --disable-all --remove-assert --infer-rw --repl-seq-mem -c:top.TopMain:-o:build/XSTop.v.conf
Preparing Java 11.0.11 runtime; this may take a minute or two ...
Compiling /home/server/repo/XiangShan/build.sc
[27/191] api-config-chipsalliance.compile
Compiling compiler interface...
[info] compiling 1 Scala source to /home/server/repo/XiangShan/out/api-config-chipsalliance/compile/dest/classes ...
[info] done compiling
[51/191] rocket-chip.macros.compile
[info] compiling 1 Scala source to /home/server/repo/XiangShan/out/rocket-chip/macros/compile/dest/classes ...
[info] done compiling
[104/191] rocket-chip.compile
[info] compiling 376 Scala sources to /home/server/repo/XiangShan/out/rocket-chip/compile/dest/classes ...
[error] /home/server/repo/XiangShan/rocket-chip/src/main/scala/tile/FPU.scala:293:25: not found: value hardfloat
[error] def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)
[error] ^
[error] /home/server/repo/XiangShan/rocket-chip/src/main/scala/tile/FPU.scala:294:23: not found: value hardfloat
[error] def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)
[error] ^
[error] /home/server/repo/XiangShan/rocket-chip/src/main/scala/tile/FPU.scala:465:25: not found: value hardfloat
[error] val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
[error] ^
[error] /home/server/repo/XiangShan/rocket-chip/src/main/scala/tile/FPU.scala:493:29: not found: value hardfloat
[error] val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))
[error] ^
[error] /home/server/repo/XiangShan/rocket-chip/src/main/scala/tile/FPU.scala:503:35: not found: value hardfloat
[error] val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))
[error] ^
[error] /home/server/repo/XiangShan/rocket-chip/src/main/scala/tile/FPU.scala:551:28: not found: value hardfloat
[error] val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))
[error] ^
[error] /home/server/repo/XiangShan/rocket-chip/src/main/scala/tile/FPU.scala:560:55: value >> is not a member of Nothing
[error] val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last
[error] ^
[error] /home/server/repo/XiangShan/rocket-chip/src/main/scala/tile/FPU.scala:560:60: value getWidth is not a member of Nothing
[error] val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last
[error] ^
[error] /home/server/repo/XiangShan/rocket-chip/src/main/scala/tile/FPU.scala:614:35: not found: value hardfloat
[error] val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))
[error] ^
[error] /home/server/repo/XiangShan/rocket-chip/src/main/scala/tile/FPU.scala:648:46: not found: value hardfloat
[error] val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
[error] ^
[error] 14 errors found
1 targets failed
rocket-chip.compile Compilation failed
Makefile:48: recipe for target 'build/XSTop.v' failed
make: *** [build/XSTop.v] Error 1

Consider to implement CoLT: Coalesced Large-Reach TLBs

http://cs.yale.edu/homes/abhishek/binhpham-micro12.pdf

make verilog 期间内存溢出导致无法生成代码

Hi, 我在工程的根目录执行 make verilog 命令生成 Verilog 代码时，出现了 java.lang.OutOfMemoryError: Java heap space 错误，看起来是内存不够用了。不过运行时使用的电脑内存有 32G，按说是够用的，而且在出现错误前从资源监视器里也能看出内存并未用光（大概只占用了70%）。在 build.sc#L84 里有个 JVM 最大内存的选项，将它修改为 -Xmx20G 后问题也还是一样。不是很清楚 Scala/mill/Chisel 运行/编译时应该怎样配置内存相关的参数，在其他地方也没找到能解决问题的方法，希望能在这里得到一些帮助~

系统是 Manjaro 21.0.3，出错时显示的调用栈如下：

L3 InclusiveCache Client Map:
	0 <= L2 InclusiveCache
	1 <= dma ID#0
	2 <= dma ID#1

[deprecated] ListBuffer.scala:153 (5 calls): do_toBools is deprecated: "Use asBools instead"
[deprecated] ListBuffer.scala:164 (5 calls): do_toBools is deprecated: "Use asBools instead"
[warn] There were 2 deprecated function(s) used. These may stop compiling in a future release - you are encouraged to fix these issues.
[warn] Line numbers for deprecations reported by Chisel may be inaccurate; enable scalac compiler deprecation warnings via either of the following methods:
[warn]   In the sbt interactive console, enter:
[warn]     set scalacOptions in ThisBuild ++= Seq("-unchecked", "-deprecation")
[warn]   or, in your build.sbt, add the line:
[warn]     scalacOptions := Seq("-unchecked", "-deprecation")
Done elaborating.
Exception in thread "main" java.lang.OutOfMemoryError: Java heap space
	at scala.collection.mutable.HashTable.resize(HashTable.scala:258)
	at scala.collection.mutable.HashTable.addEntry0(HashTable.scala:158)
	at scala.collection.mutable.HashTable.findOrAddEntry(HashTable.scala:170)
	at scala.collection.mutable.HashTable.findOrAddEntry$(HashTable.scala:167)
	at scala.collection.mutable.LinkedHashSet.findOrAddEntry(LinkedHashSet.scala:44)
	at scala.collection.mutable.LinkedHashSet.add(LinkedHashSet.scala:68)
	at scala.collection.mutable.LinkedHashSet.$plus$eq(LinkedHashSet.scala:63)
	at scala.collection.mutable.LinkedHashSet.$plus$eq(LinkedHashSet.scala:44)
	at scala.collection.generic.Growable.$anonfun$$plus$plus$eq$1(Growable.scala:62)
	at scala.collection.generic.Growable$$Lambda$12/1730173572.apply(Unknown Source)
	at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:62)
	at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:55)
	at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:49)
	at scala.collection.generic.Growable.$plus$plus$eq(Growable.scala:62)
	at scala.collection.generic.Growable.$plus$plus$eq$(Growable.scala:53)
	at scala.collection.mutable.AbstractSet.$plus$plus$eq(Set.scala:48)
	at scala.collection.mutable.SetLike.$plus$plus(SetLike.scala:191)
	at scala.collection.mutable.SetLike.$plus$plus$(SetLike.scala:191)
	at scala.collection.mutable.AbstractSet.$plus$plus(Set.scala:48)
	at firrtl.graph.DiGraph.getVertices(DiGraph.scala:57)
	at firrtl.transforms.DeadCodeElimination.run(DeadCodeElimination.scala:347)
	at firrtl.transforms.DeadCodeElimination.execute(DeadCodeElimination.scala:386)
	at firrtl.Transform.transform(Compiler.scala:319)
	at firrtl.Transform.transform$(Compiler.scala:319)
	at firrtl.transforms.DeadCodeElimination.transform(DeadCodeElimination.scala:33)
	at firrtl.stage.transforms.ExpandPrepares.execute(ExpandPrepares.scala:19)
	at firrtl.Transform.transform(Compiler.scala:319)
	at firrtl.Transform.transform$(Compiler.scala:319)
	at firrtl.stage.transforms.ExpandPrepares.transform(ExpandPrepares.scala:7)
	at firrtl.stage.transforms.CatchCustomTransformExceptions.execute(CatchCustomTransformExceptions.scala:10)
	at firrtl.Transform.transform(Compiler.scala:319)
	at firrtl.Transform.transform$(Compiler.scala:319)
1 targets failed
XiangShan.test.runMain subprocess failed
make: *** [Makefile:49: build/XSTop.v] Error 1

另外我在 GitHub Actions 上也试着跑了下，也会出现类似的错误，不过栈信息不太一样，可以在这里看到完整的日志。

logutils: 需要一些改进

(1) 需要支持对特定时间范围内的log打印
实现上，只需要在XSlog里面cond加入条件即可

(2) 需要支持对特定模块log打印，在代码中唯一的地方选择部分模块进行打印，能够开关每一个模块的打印。
具体实现上，可以通过对模块的选择来做。

关于freelist的问题

rename模块中的freelist是一个128项的环形队列，freelist中放置可使用的free reg，headPtr指向头，从headPtr开始分配，把free reg分配给指令；tailPtr指向尾，释放的reg从tailPtr重新加入freelist。正常情况两者同时往前走，当然tailPtr不能超越headPtr，但是因为存在mispredict的情况，headPtr某些情况下需要回滚。这样似乎会带来一个问题，假如headPtr和tailPtr靠的比较近，当headPtr需要回滚到位置x时，却发现x已经被tailPtr超越，即本来准备回滚重新分配的freelist值，已经被释放的reg值覆盖了，这些值将永远无法重新在freelist中出现。此时虽然core可以继续运作，但是实际上部分物理reg已经泄露，无法被再分配了。
不知道我理解的是否正确，这种场景是否会出现？
谢谢！

make verilog 失败

环境为 ubuntu 18.04，按照 readme.md 中，先 git clone，再 make init，再 make verilog，反复尝试多次均会报错。
没有出现 java exception，看起来与现有的其他 issue 均不是同一个问题。

输出如下：
`mkdir -p build
mill XiangShan.runMain top.TopMain -td build
--config DefaultConfig --full-stacktrace --output-file XSTop.v
--disable-all --remove-assert --infer-rw
--repl-seq-mem -c:top.TopMain:-o:build/XSTop.v.conf
--num-cores 1
[191/191] XiangShan.runMain
Elaborating design...
FPGASoC cores: 1 banks: 4 block size: 64 bus size: 256
INT Regfile: 14R8W
FP Regfile: 14R8W
RS 0: type AluExeUnit, size 64, enq 4, deq 4, numSrc 2, fast 8, wakeup 8
RS 1: type MulDivExeUnit, size 32, enq 4, deq 2, numSrc 2, fast 6, wakeup 8
RS 2: type JmpExeUnit, size 16, enq 1, deq 1, numSrc 2, fast 6, wakeup 8
RS 3: type FmacExeUnit, size 64, enq 4, deq 4, numSrc 3, fast 4, wakeup 8
RS 4: type FmiscExeUnit, size 32, enq 4, deq 2, numSrc 2, fast 4, wakeup 8
RS 5: type LoadExu, size 16, enq 1, deq 1, numSrc 1, fast 8, wakeup 8
RS 6: type LoadExu, size 16, enq 1, deq 1, numSrc 1, fast 8, wakeup 8
RS 7: type StoreExu, size 16, enq 1, deq 1, numSrc 2, fast 6, wakeup 16
RS 8: type StoreExu, size 16, enq 1, deq 1, numSrc 2, fast 6, wakeup 16
Scheduler:
number of issue ports: 17
number of replay ports: 4
number of std ports: 2
number of outside fast wakeup ports: 2
[WARN] Signal |DISPLAY_LOG_ENABLE| has multiple sinks
[WARN] Signal |logTimestamp| has multiple sinks
ImmUnion max len: 20
LoadQueue: size:64
StoreQueue: size:48
Regfile: size:160 read: 14write: 8
Regfile: size:160 read: 14write: 8
Fast wakeup: RS 0 -> List(0, 1, 2, 5, 6, 7, 8), source: [0,4)
Fast wakeup: RS 1 -> List(0, 1, 2, 5, 6, 7, 8), source: [6,8)
Fast wakeup: RS 3 -> List(3, 4), source [8, 12)
Fast wakeup: RS 5 -> List(0, 5, 6), source: [4,5)
Fast wakeup: RS 6 -> List(0, 5, 6), source: [5,6)
FPGAPlatform:true EnableDebug:true

Memory map:
[h00_0000_0000 -> h00_0FFF_FFFF] Width:unlimited Description:Reserved [RW]
[h00_1000_0000 -> h00_1FFF_FFFF] Width:unlimited Description:QSPI_Flash [RWX]
[h00_2000_0000 -> h00_2FFF_FFFF] Width:unlimited Description:Reserved [RW]
[h00_3000_0000 -> h00_3000_FFFF] Width:unlimited Description:DMA [RW]
[h00_3001_0000 -> h00_3004_FFFF] Width:unlimited Description:GPU [RWC]
[h00_3005_0000 -> h00_3006_FFFF] Width:unlimited Description:USB/SDMMC [RW]
[h00_3007_0000 -> h00_30FF_FFFF] Width:unlimited Description:Reserved [RW]
[h00_3100_0000 -> h00_3111_FFFF] Width:unlimited Description:MMIO [RW]
[h00_3112_0000 -> h00_37FF_FFFF] Width:unlimited Description:Reserved [RW]
[h00_3800_0000 -> h00_3800_FFFF] Width:unlimited Description:CLINT [RW]
[h00_3801_0000 -> h00_3801_FFFF] Width:unlimited Description:BEU [RW]
[h00_3802_0000 -> h00_3BFF_FFFF] Width:unlimited Description:Reserved []
[h00_3C00_0000 -> h00_3FFF_FFFF] Width:unlimited Description:PLIC [RW]
[h00_4000_0000 -> h00_7FFF_FFFF] Width:unlimited Description:PCIe [RW]
[h00_8000_0000 -> h1F_FFFF_FFFF] Width:unlimited Description:DDR [RWXIDSA]

Ftq: size:48
Roq: size:192 wbports:18 commitwidth:6
CSR: hasEmuPerfCnt:false

int wb arbiter:
[ AluExeUnit ] -> out #0
[ AluExeUnit ] -> out #1
[ AluExeUnit ] -> out #2
[ AluExeUnit ] -> out #3
[ LoadExu ] -> out #4
[ LoadExu ] -> out #5
[ MulDivExeUnit JmpExeUnit ] -> arb -> out #6
[ MulDivExeUnit FmiscExeUnit FmiscExeUnit ] -> arb -> out #7

1 targets failed
XiangShan.runMain subprocess failed
Makefile:49: recipe for target 'build/XSTop.v' failed
make: *** [build/XSTop.v] Error 1`

分支预测优化点

• BTB空间利用率提高 #1163
• 间接跳转预测器 #992
• RAS溢出的处理 #748
• 分支历史的筛选 #986
• BIM迟滞位共享
• TAGE实现IUM
• TAGE实现IMLI
• TAGE使用更长的历史 #1390
• 取指和预测解耦 #986
• TAGE使用折叠历史 #1223

对飞线的管理

目前的代码中有许多使用BoringUtils进行飞线连接的地方，使用这些飞线的目的大致可以分为3类：
1.跨模块传递Debug信号
2.接性能计数器
3.简化模块间连线

由于BoringUtils并没有一个集中管理飞线的地方，许多使用了飞线连接的模块被删除/修改后难以发现错误，例如：
1.如果Source被删除，Sink不会报错，但Sink的值永远不会被Source更新
2.如果Sink被删除，代码编译会报错，如果代码中有多个Sink被删除，只能根据报错信息一个一个寻找，调试效率很低

基于上述原因，需要一个模块对所有飞线统一管理，并能提供API查询代码中存在的所有飞线

make verilog error

我的环境是debian，按照说明git clone了本项目，然后执行make init，然后执行make verilog，报错如下：请赐教，感谢！
make verilog
mkdir -p build
mill XiangShan.test.runMain top.TopMain -td build --config DefaultConfig --full-stacktrace --output-file XSTop.v --disable-all --remove-assert --infer-rw --repl-seq-mem -c:top.TopMain:-o:build/XSTop.v.conf
[104/212] rocket-chip.compile
[info] compiling 376 Scala sources to
... ^
[error] 14 errors found
1 targets failed
rocket-chip.compile Compilation failed
make: *** [Makefile:52: build/XSTop.v] Error 1

full install step share

#risc-v cpu full project, I use root login ubuntu 16.04
apt install verilog
sh -c "curl -L https://github.com/com-lihaoyi/mill/releases/download/0.9.9/0.9.9 > /usr/local/bin/mill && chmod +x /usr/local/bin/mill"
mill version

mkdir -p /root/riscv_cpu
cd /root/riscv_cpu

git clone --recursive https://github.com/OpenXiangShan/NEMU.git
git clone --recursive https://github.com/OpenXiangShan/nexus-am.git
git clone --recursive https://github.com/OpenXiangShan/XiangShan.git
git clone --recursive https://github.com/verilator/verilator

#absolute path
export NEMU_HOME="/root/riscv_cpu/NEMU"
export AM_HOME="/root/riscv_cpu/nexus-am"
export NOOP_HOME="/root/riscv_cpu/XiangShan"

cd verilator
autoconf
./configure
make -j8 && make install

cd /root/riscv_cpu/XiangShan
make init

gedit /root/riscv_cpu/XiangShan/build.sc
#find all
-Xmx64G
#change to
-Xmx16G
(my pc is 16g ram 16g swap ubuntu 16.04.7)

#generate .v
make verilog -j8

#simulation
make emu CONFIG=MinimalConfig SIM_ARGS=--disable-log EMU_THREADS=2 -j8
./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so

Refer to: https://fatalfeel.blogspot.com/2013/12/chisel-design-ic-for-risc-v.html

coremark pass

2020.7.6 coremark pass, #94

Add this core to chipyard

Chipyard is a RISC-V SoC chisel framework. Since this core is also in chisel and open source, I think it is natural to add this core in chipyard. Is it possible to have it in chipyard? Will it be useful for chipyard and/or xiangshan and worth the needed efforts? I think it makes community of open source RISC-V cores more engaged in XiangShan.

cputest pass

2020.7.6 cputest pass, see #93

关于icache中predecode的问题

val pds = Seq.fill(nWays)(Module(new PreDecode))
for (i <- 0 until nWays) {
val wayResp = Wire(new ICacheResp)
val wayData = cutHelper(s3_data(i), s3_req_pc, s3_req_mask)
val refillData = Mux(s3_sec_miss,cutHelper(refillDataVecReg, s3_req_pc,s3_req_mask),cutHelper(refillDataVec, s3_req_pc,s3_req_mask))
wayResp.pc := s3_req_pc
wayResp.data := Mux(s3_valid && s3_hit, wayData, Mux(s3_mmio ,mmio_packet ,refillData))
wayResp.mask := s3_req_mask
wayResp.ipf := s3_exception_vec(pageFault)
wayResp.acf := s3_exception_vec(accessFault)
wayResp.mmio := s3_mmio
pds(i).io.in := wayResp
pds(i).io.prev <> io.prev
pds(i).io.prev_pc := io.prev_pc
}

io.pd_out := Mux1H(s3_wayMask, pds.map(_.io.out))

icache的设计中针对每一个way都实例化了一个predecode，但是其实每次只会有1个hit way，按道理应该通过s3_wayMask筛选一下，然后只针对真正的hit way来做predecode。
不知道现在这个设计有什么特殊的考虑？谢谢

regfile写口仲裁

writeback arbiter现在是空的，需要完善。

6/26：debug的时候直接把alu 0-3(对应功能单元index 1-4)接到了输出上面，没有做仲裁。

A fast CI is what we need

Though running simulations in hardware development is relatively slow compared to software developments, a faster CI could surely save time and encourage more people to contribute and to contribute more to the XiangShan project.

For example, my PR (#850 ) merely made some typo fixes, but it still consumed almost 1 hour to run and rerun (CI may fail unexpectedly even the code is actually correct).

Taking a look into tests, a time-consuming operation build EMU ran twice in different tests, if the simulator could be reused, it'll save some time for us.

Improve could be made by:

1. better machine running tests, even better than GitHub Actions, this might cost lots of money and power.
2. adapt the way how CI runs, maybe like what I said above.

Though hard making improvement might be, once it being made, there'll be a leap in contributing experience.

considering how much people might come here to contribute, better come along with more marketing works.

how can I debug ALU scala in idea

I want to debug rocket scala in idea, how do I do
Ex: ALU

in this dir
https://github.com/OpenXiangShan/rocket-chip/tree/c7da610430f51b02ebda37f3d444674dc8f2adbf/src/main/scala/rocket

how do I do?

添加中文README和文档

就当出来划水，搬砖去了，告辞

xiangshan compile error

after make init, i try to run and get failure:

../mill/mill XiangShan.runMain top.TopMain -td build --config DefaultConfig --full-stacktrace --output-file XSTop.v   --disable-all --remove-assert --infer-rw --repl-seq-mem -c:top.TopMain:-o:build/XSTop.v.conf --num-cores 4

i got following log:

Exception in thread "main" chisel3.internal.ChiselException: Connection between sink (Bool[1](IO io_hartIsInReset in TLDebugModule)) and source (Bool[4](IO in unelaborated DebugModule)) failed @: Sink and Source are different length Vecs.
        at chisel3.internal.throwException$.apply(Error.scala:155)
        at chisel3.Data.connect(Data.scala:416)
        at chisel3.Vec.$colon$eq(Aggregate.scala:237)
        at device.DebugModule$$anon$1.<init>(RocketDebugWrapper.scala:64)
        at device.DebugModule.module$lzycompute(RocketDebugWrapper.scala:55)
        at device.DebugModule.module(RocketDebugWrapper.scala:55)
        at device.DebugModule.module(RocketDebugWrapper.scala:41)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$2(LazyModule.scala:278)
        at chisel3.Module$.do_apply(Module.scala:54)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$1(LazyModule.scala:278)
        at scala.collection.immutable.List.flatMap(List.scala:338)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate(LazyModule.scala:276)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate$(LazyModule.scala:273)
        at freechips.rocketchip.diplomacy.LazyRawModuleImp.instantiate(LazyModule.scala:344)
        at freechips.rocketchip.diplomacy.LazyRawModuleImp.$anonfun$x$22$1(LazyModule.scala:357)
        at chisel3.withClockAndReset$.apply(MultiClock.scala:25)
        at freechips.rocketchip.diplomacy.LazyRawModuleImp.<init>(LazyModule.scala:357)
        at top.XSTopWithoutDMA$$anon$5.<init>(Top.scala:371)
        at top.XSTopWithoutDMA.module$lzycompute(Top.scala:371)
        at top.XSTopWithoutDMA.module(Top.scala:371)
        at top.TopMain$.$anonfun$main$1(Top.scala:454)
        at chisel3.Module$.do_apply(Module.scala:54)
        at chisel3.stage.ChiselGeneratorAnnotation.$anonfun$elaborate$1(ChiselAnnotations.scala:60)
        at chisel3.internal.Builder$.$anonfun$build$1(Builder.scala:656)
        at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)
        at chisel3.internal.Builder$.build(Builder.scala:653)
        at chisel3.internal.Builder$.build(Builder.scala:649)
        at chisel3.stage.ChiselGeneratorAnnotation.elaborate(ChiselAnnotations.scala:60)
        at chisel3.stage.phases.Elaborate.$anonfun$transform$1(Elaborate.scala:26)
        at scala.collection.TraversableLike.$anonfun$flatMap$1(TraversableLike.scala:245)
        at scala.collection.immutable.List.foreach(List.scala:392)
        at scala.collection.TraversableLike.flatMap(TraversableLike.scala:245)
        at scala.collection.TraversableLike.flatMap$(TraversableLike.scala:242)
        at scala.collection.immutable.List.flatMap(List.scala:355)
        at chisel3.stage.phases.Elaborate.transform(Elaborate.scala:24)
        at chisel3.stage.phases.Elaborate.transform(Elaborate.scala:17)
        at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
        at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
        at firrtl.options.Translator.transform(Phase.scala:248)
        at firrtl.options.Translator.transform$(Phase.scala:248)
        at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
        at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:278)
        at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)
        at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)
        at scala.collection.immutable.List.foldLeft(List.scala:89)
        at firrtl.options.DependencyManager.transform(DependencyManager.scala:269)
        at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255)
        at firrtl.options.PhaseManager.transform(DependencyManager.scala:436)
        at chisel3.stage.ChiselStage.run(ChiselStage.scala:45)
        at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
        at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
        at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
        at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
        at firrtl.options.Translator.transform(Phase.scala:248)
        at firrtl.options.Translator.transform$(Phase.scala:248)
        at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
        at firrtl.options.Stage.$anonfun$transform$5(Stage.scala:47)
        at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)
        at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)
        at scala.collection.immutable.List.foldLeft(List.scala:89)
        at firrtl.options.Stage.$anonfun$transform$3(Stage.scala:47)
        at logger.Logger$.$anonfun$makeScope$2(Logger.scala:166)
        at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)
        at logger.Logger$.makeScope(Logger.scala:164)
        at firrtl.options.Stage.transform(Stage.scala:47)
        at firrtl.options.Stage.execute(Stage.scala:58)
        at top.XiangShanStage$.execute(XiangShanStage.scala:49)
        at top.TopMain$.main(Top.scala:452)
        at top.TopMain.main(Top.scala)
1 targets failed
XiangShan.runMain subprocess failed
java.io.IOException: com.sun.jna.LastErrorException: [104] Connection reset by peer
        at org.scalasbt.ipcsocket.UnixDomainSocket$UnixDomainSocketInputStream.doRead(UnixDomainSocket.java:151)
        at org.scalasbt.ipcsocket.UnixDomainSocket$UnixDomainSocketInputStream.read(UnixDomainSocket.java:122)
        at mill.main.client.ProxyStreamPumper.run(ProxyStreamPumper.java:23)
        at java.lang.Thread.run(Thread.java:748)
Caused by: com.sun.jna.LastErrorException: [104] Connection reset by peer
        at org.scalasbt.ipcsocket.UnixDomainSocketLibrary.read(Native Method)
        at org.scalasbt.ipcsocket.UnixDomainSocket$UnixDomainSocketInputStream.doRead(UnixDomainSocket.java:149)
        ... 3 more

重命名表初始化与后续维护存在问题

现在的重命名表全部初始化为0，同时所有物理寄存器均在freelist中，同时没有对0号寄存器做特殊处理。
这会导致在rename分配0号物理寄存器后，dispatch2阶段发现源操作数(初始为0号)是busy状态，等待写回，因此指令被一直堵在保留站中无法发射。

mill installation method has expired

I can't install mill in my ubuntu

env配置的仓库路径不对

rocket-chip下面的torture配置的env路径是：
[submodule "env"]
path = env
url = git://github.com/ucb-bar/riscv-test-env.git

而env实际上是在riscv仓库下面，导致git init下载失败。

can you make a version for IntelliJ

can you make a version for IntelliJ

OpenJDK 64-Bit Server问题

make verilog/make emu出现如下问题：

Connection:[DISPLAY_LOG_ENABLE] type:[func] source location:[SimTop] sink location:[AXI4RAM_1]
Connection:[logTimestamp] type:[func] source location:[SimTop] sink location:[AXI4RAM_1]
Connection:[XSPERF_CLEAN] type:[func] source location:[SimTop] sink location:[L2Prefetcher]
Connection:[XSPERF_DUMP] type:[func] source location:[SimTop] sink location:[L2Prefetcher]
[deprecated] ListBuffer.scala:153 (5 calls): do_toBools is deprecated: "Use asBools instead"
[deprecated] ListBuffer.scala:164 (5 calls): do_toBools is deprecated: "Use asBools instead"
[warn] There were 2 deprecated function(s) used. These may stop compiling in a future release - you are encouraged to fix these issues.
[warn] Line numbers for deprecations reported by Chisel may be inaccurate; enable scalac compiler deprecation warnings via either of the following methods:
[warn]   In the sbt interactive console, enter:
[warn]     set scalacOptions in ThisBuild ++= Seq("-unchecked", "-deprecation")
[warn]   or, in your build.sbt, add the line:
[warn]     scalacOptions := Seq("-unchecked", "-deprecation")
Done elaborating.
#
�# There is insufficient memory for the Java Runtime Environment to continue.
# Native memory allocation (mmap) failed to ma 69�62544640 bytes for committing reserved memory.
# An error report file with more information is saved as:
# /home/usrname/Projec!ts/XiangShan/hs_err_pid26575.log
OpenJDK 64-Bit Server VM warning: INFO: os::commit_mmory(0x00007f4e9d000000, 6962544640, 0) failed; error='Not enough space' (�errno=12)
�1 targets Makefile:79: recipe for target 'build/SimTop.v' failed
make: *** [build/SimTop.v] Error 1

如果将

./build.sc:84:  override def forkArgs = Seq("-Xmx64G")
./build.sc:95:    override def forkArgs = Seq("-Xmx64G")
./out/XiangShan/test/forkArgs/meta.json:3:        "-Xmx64G"
./out/XiangShan/forkArgs/meta.json:3:        "-Xmx64G"

这些文件中的 jvm_args: -Xmx64G 改小点则可以通过，希望这个参数用户可配

正确的log文件如下：

[warn] There were 2 deprecated function(s) used. These may stop compiling in a future release - you are encouraged to fix these issues.
[warn] Line numbers for deprecations reported by Chisel may be inaccurate; enable scalac compiler deprecation warnings via either of the following methods:
[warn]   In the sbt interactive console, enter:
[warn]     set scalacOptions in ThisBuild ++= Seq("-unchecked", "-deprecation")
[warn]   or, in your build.sbt, add the line:
[warn]     scalacOptions := Seq("-unchecked", "-deprecation")
Done elaborating.




（＊好久＊）




xiangshan.backend.MemBlock@102db955
java.io.IOException: com.sun.jna.LastErrorException: [104] 连接被对方重设
./scripts/vlsi_mem_gen build/XSTop.v.conf --tsmc28 --output_file build/tsmc28_sram.v > build/tsmc28_sram.v.conf
./scripts/vlsi_mem_gen build/XSTop.v.conf --output_file build/sim_sram.v
# sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' build/XSTop.v

make emu failed: java.io.IOException: com.sun.jna.LastErrorException

运行代码 make emu CONFIG=MinimalConfig SIM_ARGS=--disable-log EMU_THREADS=2 -j10

出现如下错误

Done elaborating.
1 targets failed
XiangShan.test.runMain subprocess failed
java.io.IOException: com.sun.jna.LastErrorException: [104] 连接被对方重设
	at org.scalasbt.ipcsocket.UnixDomainSocket$UnixDomainSocketInputStream.doRead(UnixDomainSocket.java:151)
	at org.scalasbt.ipcsocket.UnixDomainSocket$UnixDomainSocketInputStream.read(UnixDomainSocket.java:122)
	at mill.main.client.ProxyStreamPumper.run(ProxyStreamPumper.java:23)
	at java.base/java.lang.Thread.run(Thread.java:829)
Caused by: com.sun.jna.LastErrorException: [104] 连接被对方重设
	at org.scalasbt.ipcsocket.UnixDomainSocketLibrary.read(Native Method)
	at org.scalasbt.ipcsocket.UnixDomainSocket$UnixDomainSocketInputStream.doRead(UnixDomainSocket.java:149)
	... 3 more
make: *** [Makefile:82：build/SimTop.v] 错误 1

Makefile:78～94为

$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
        mkdir -p $(@D)
        @echo "\n[mill] Generating Verilog files..." > $(TIMELOG)
        @date -R | tee -a $(TIMELOG)
        $(TIME_CMD) mill XiangShan.test.runMain $(SIMTOP) -td $(@D)      \
                --config $(CONFIG) --full-stacktrace --output-file $(@F)     \
                --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf   \
                --num-cores $(NUM_CORES) $(SIM_ARGS)
        $(MEM_GEN) $(@D)/$(@F).conf --output_file $(@D)/$(@F).sram.v
        @git log -n 1 >> .__head__
        @git diff >> .__diff__
        @sed -i 's/^/\/\// ' .__head__
        @sed -i 's/^/\/\//' .__diff__
        @cat .__head__ .__diff__ $@ $(@D)/$(@F).sram.v > .__out__
        @mv .__out__ $@
        @rm .__head__ .__diff__
        sed -i -e 's/$$fatal/xs_assert(`__LINE__)/g' $(SIM_TOP_V)

第82行为：

$(TIME_CMD) mill XiangShan.test.runMain $(SIMTOP) -td $(@D) \

java -version

openjdk version "11.0.11" 2021-04-20
OpenJDK Runtime Environment (build 11.0.11+9-Ubuntu-0ubuntu2.20.04)
OpenJDK 64-Bit Server VM (build 11.0.11+9-Ubuntu-0ubuntu2.20.04, mixed mode, sharing)

我百度了一下，或许是因为我的java版本不匹配？请问这个错误该怎么解决呢？