%Error: build/SimTop.v:2487721:3: Cannot find file containing module: 'array_18_ext' about xiangshan

[poemonsense]

For SRAMs, currently Chisel generates SRAM via verilog blackboxes. A python script is used to generate these SRAM modules with names starting with array_*. This step is done after the mill/scala process. We will remove the script after Chisel updates the transforms to include vlsi_mem_gen (issue #858).

Cannot find file containing module happens when make stops before the script runs due to some errors, in which case the SRAM modules are not generated.

To solve this, please try to manually run the following command, which is also in the Makfile

./scripts/vlsi_mem_gen build/SimTop.v.conf --output_file build/SimTop.v.sram.v
cat build/SimTop.v build/SimTop.v.sram.v > .__out__
mv .__out__ build/SimTop.v

If the above does not work, please try

rm -rf build
# make again here

[liliwenaaa]

For SRAMs, currently Chisel generates SRAM via verilog blackboxes. A python script is used to generate these SRAM modules with names starting with array_*. This step is done after the mill/scala process. We will remove the script after Chisel updates the transforms to include vlsi_mem_gen (issue #858).

Cannot find file containing module happens when make stops before the script runs due to some errors, in which case the SRAM modules are not generated.

To solve this, please try to manually run the following command, which is also in the Makfile

./scripts/vlsi_mem_gen build/SimTop.v.conf --output_file build/SimTop.v.sram.v
cat build/SimTop.v build/SimTop.v.sram.v > .__out__
mv .__out__ build/SimTop.v

If the above does not work, please try

rm -rf build
# make again here

get error
./scripts/vlsi_mem_gen build/SimTop.v.conf --output_file build/SimTop.v.sram.v
File "./scripts/vlsi_mem_gen", line 28
self.port_spec.append(f'{io_type} {width_str}{name}')
^
SyntaxError: invalid syntax

[sequencer]

Google plz: fstring

[liliwenaaa]

Problem in my python version，pyhton3.6 replace python3.5