henry-czh Goto Github PK

cbs_gui

cbs_smt

cbs simulate manager tool

chisel3

Chisel 3: A Modern Hardware Design Language

dokuwiki

The DokuWiki Open Source Wiki Engine

flash-linux0.11-talk

你管这破玩意叫操作系统源码 — 像小说一样品读 Linux 0.11 核心代码

fsdb_editor

gem5

This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.

gem5_arm_fullsystem_files_generator

Generator of kernels, bootloaders, DTBs and disk images for aarch32 and aarch64 gem5 Full System simulations (updated April 2018)

gen_amba_2021

AMBA bus generator including AXI4, AXI3, AHB, and APB

greenlib

GreenLib official mirror, please use git.greensocs.com for issues and contributions

henry-czh

Config files for my GitHub profile.

hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

libsystemctlm-soc

SystemC/TLM-2.0 Co-simulation framework

linux

Linux kernel source tree

linux-0.12

赵炯老师《linux-0.12 内核完全剖析》读书笔记及linux-0.12注释源码

lite_regmodel

lite regmodel for SOC verification

livesp

The aim is making every SimPoint of one program runnable without simulator. It means each SimPoint will be made into an completely independent binary program.

lmac_core2

LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G

partial_access_tool

portable-stimulus

pssparser

ANTLR-based implementation of an Accellera PSS language parser with C++ and Python interfaces

riffa

The RIFFA development repository

rocket-chip

Rocket Chip Generator

soc_chip_tb_cfg_mgt

The configuration managment of chip level testbench of soc.

spider

sys_env

SOC system verification testbench

systemc-components

A SystemC productivity library for virtual platform development utilizing SCV and TLM2.0

systemctlm-cosim-demo

systemverilog-training

Some examples of systemverilog for training

tinyc

https://pandolia.net/tinyc/