lauchinyuan's Projects
asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counter.
A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
python_data_analysis
Some FPGA module, e.g., Direct Digital Synthesizer and NEC Infrared Protocol Decoder, written in Verilog HDL.
An AXI DDR3 SDRAM controller for FPGA
A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA
My github profile
My blog Pages
C++ coursework written in 2020, accompanied by a report written in Chinese
temporary log repository
ML learning
some code during learning python
Simple Python code written during the process of learning PyTorch
Using pytorch to realize neural network quantization, parameter export and FPGA/ASIC fixed-point arithemetic simulation
Reed Solomon encoder written in verilog hardware description language
Simple SDRAM controller written in Verilog hardware description language
simple STM32 project with LCD and some sensors
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A simple RISC-V core
A configurable image processing module, its functions include image grayscale, RGB to HSV, etc.
Open-source high-performance RISC-V processor