Topic: chisel Goto Github
Some thing interesting about chisel
Some thing interesting about chisel
chisel,A hardware rasterizer created for real-time rendering
User: alanjian85
chisel,Establish a Reverse Tunnel between different servers and clients. IPV4 | IPV6 - Supports TCP & UDP . You can establish a tunnel between 5 Kharej servers & 1 IRAN server and vice versa.
User: azumi67
chisel,Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
Organization: bu-icsg
chisel,Chisel: A Modern Hardware Design Language
Organization: chipsalliance
Home Page: https://www.chisel-lang.org/
chisel,Rocket Chip Generator
Organization: chipsalliance
chisel,A dynamic verification library for Chisel.
Organization: chiselverify
chisel,Provides dot visualizations of chisel/firrtl circuits
Organization: freechipsproject
chisel,Kubernetes Operator for Chisel
Organization: fyralabs
Home Page: https://chisel.fyralabs.com
chisel,『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ
User: horie-t
chisel,Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"
User: horie-t
chisel,Implementation of the Advanced Encryption Standard in Chisel
Organization: hplp
chisel,FFT generator using Chisel
Organization: ia-c-lab-fudan
chisel,A fault-injection framework using Chisel and FIRRTL
Organization: ibm
chisel,Support files for participating in a Fomu workshop
Organization: im-tomu
Home Page: https://workshop.fomu.im
chisel,Various examples for Chisel HDL
User: j-marjanovic
chisel,Quasar 2.0: Chisel equivalent of SweRV-EL2
Organization: lampro-mellon
chisel,A .NET XOR encrypted cobalt strike aggressor implementation for chisel to utilize faster proxy and advanced socks5 capabilities.
User: m3rcer
Home Page: https://github.com/m3rcer/Chisel-Strike
chisel,Chisel components for FPGA projects
User: maltanar
chisel,:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
Organization: microdynamics-cpu
chisel,A tool to create HTTPS reverse tunnels
Organization: nextchaptersoftware
chisel,Open-source high-performance RISC-V processor
Organization: openxiangshan
chisel,All-in-one OPIran scripts
User: opiran-club
chisel,Work in progress prototype for the Chisel Level Editor, for Unity
Organization: radicalcsg
chisel,A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code to values dumped by simulators is now possible thanks to Tywaves!
User: rameloni
chisel,SonicBOOM: The Berkeley Out-of-Order Machine
Organization: riscv-boom
chisel,Personal CheatSheet used for the exam made with Obsidian, download the repo and use the resources within Obsidian for a better experience. CHISEL & SOCAT BINARIES ARE WITHIN THE PIVOTING SECTION.
User: sergiovks
chisel,A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
User: starrynightzyq
chisel,🛠 lldb, breakpoint, shortcut 등을 이용한 생산성 향상 방법을 배워보자 🛠
User: sujinnaljin
chisel,A compact guide to network pivoting for penetration testings / CTF challenges.
User: t3l3machus
chisel,Chisel library for Unum Type-III Posit Arithmetic
Organization: thoughtworks
chisel,An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Organization: ucb-bar
Home Page: https://chipyard.readthedocs.io/en/stable/
chisel,The batteries-included testing and formal verification library for Chisel-based RTL designs.
Organization: ucb-bar
chisel,A Chisel RTL generator for network-on-chip interconnects
Organization: ucb-bar
Home Page: http://constellation.readthedocs.io
chisel,Chisel RISC-V Vector 1.0 Implementation
Organization: ucb-bar
chisel,[AFK] Hardware router in Chisel (THU Network Joint Lab 2020)
User: wangrunji0408
Home Page: https://lab.cs.tsinghua.edu.cn/router/doc/joint/
chisel,一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .
User: wataru030-xiaohei
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