Topic: hdl Goto Github

👇 Here are 573 public repositories matching this topic...

1801bm1 / cpu11
hdl,Revengineered ancient PDP-11 CPUs, originals and clones
User: 1801bm1
cpucore engineering hdl pdp-11 retrocomputing reverse verilog

aappleby / metroboy
hdl,A repository of gate-level simulators and tools for the original Game Boy.
User: aappleby
verilog gameboy gameboy-emulator simulator emulator hdl

aappleby / metron
hdl,A C++ to Verilog translation tool with some basic guarantees that your code will work.
User: aappleby
fpga hdl verilog compiler transpiler c cpp

adibis / ddr2_controller
hdl,DDR2 memory controller written in Verilog
User: adibis
verilog verilog-project ddr hdl

amaranth-lang / amaranth
hdl,A modern hardware definition language and toolchain based on Python
Organization: amaranth-lang
Home Page: https://amaranth-lang.org/docs/amaranth/
fpga hdl amaranth-hdl

analogdevicesinc / hdl
hdl,HDL libraries and projects
Organization: analogdevicesinc
Home Page: https://wiki.analog.com/resources/fpga/docs/hdl
analog-devices hdl jesd204b verilog fpga hacktoberfest

analogdevicesinc / m2k-fw
hdl,M2k firmware for the ADALM-2000 Active Learning Module
Organization: analogdevicesinc
m2k adalm-2000 iio oscilloscope logic-analyzer signal-generation network-analyzer spectrum-analyzer active-learning-module fpga

analogdevicesinc / plutosdr-fw
hdl,PlutoSDR Firmware
Organization: analogdevicesinc
plutosdr adalm-pluto sdr iio active-learning-module fpga hdl linux rf transceiver

ashishrana160796 / verilog-starter-tutorials
hdl,Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
User: ashishrana160796
hdl verilog circuit switches iverilog verilog-hdl up-for-grabs beginner-friendly logic-gates practice

asyncvlsi / act
hdl,ACT hardware description language and core tools.
Organization: asyncvlsi
Home Page: http://avlsi.csl.yale.edu/act
hardware-description-language asynchronous-vlsi eda vlsi-cad asynchronous-circuits cad hdl circuit-simulator design-automation vlsi

bogdanvuk / pygears
hdl,HW Design: A Functional Approach
User: bogdanvuk
Home Page: https://www.pygears.org
hardware design python functional hdl simulator fpga asic

brianhginc / brianhg-ddr3-controller
hdl,DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
User: brianhginc
ddr3 verilog systemverilog altera intel lattice xilinx testbenches fpga hdl

catkira / open5g_phy
hdl,A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog
User: catkira
5g 5g-nr 5g-simulation fpga hdl verilog

chipsalliance / sv-tests
hdl,Test suite designed to check compliance with the SystemVerilog standard.
Organization: chipsalliance
Home Page: https://chipsalliance.github.io/sv-tests-results/
systemverilog symbiflow verilog hdl rtl compliance-testing

codingonion / awesome-cuda-tensorrt-fpga
hdl,🔥🔥🔥 A collection of some awesome public NVIDIA CUDA, cuBLAS, cuDNN, TensorRT, AMD ROCm and FPGA projects.
User: codingonion
fpga hdl yolo yolov5 cuda rocm gemm cublas cudnn tensorrt awesome rust llm sora gpu nvidia yolov8 large-language-models mojo llama3

davidthings / hdelk
hdl,Web-based HDL diagramming tool
User: davidthings
Home Page: https://davidthings.github.io/hdelk/
elkjs diagrams javascript browser hdl fpga graphs nodes edges hdelk

dfianthdl / dfiant
hdl,DFiant: A Dataflow Hardware Descripition Language
Organization: dfianthdl
Home Page: https://dfianthdl.github.io/
asic dataflow dataflow-programming fpga hdl

dpretet / async_fifo
hdl,A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
User: dpretet
verilog verification verilog-hdl icarus-verilog fifo fifo-queue fifo-cache synthesis hdl fpga

drom / awesome-hdl
hdl,Hardware Description Languages
User: drom
awesome awesome-list hardware-description-language verilog vhdl hdl hacktoberfest

f4pga / f4pga-arch-defs
hdl,FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Organization: f4pga
Home Page: https://f4pga.org
fpga ice40 sphinx documentation verilog hdl xilinx-fpga artix kintex7 architecture-definitions

furrtek / siliconre
hdl,Custom chips reverse-engineered from silicon
User: furrtek
taito reverse-engineering silicon asic chip arcade decap verilog hdl cpld

gateware-ts / gateware-ts
hdl,Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools
Organization: gateware-ts
Home Page: https://gateware-ts.github.io/gateware-ts
gateware typescript verilog hdl hardware simulation fpga

google / pcbdl
hdl,PCB Design Language: A programming way to design schematics.
Organization: google
python eda hdl electronics netlist hardware schematics

hell03end / verilog-uart
hdl,Simple 8-bit UART realization on Verilog HDL.
User: hell03end
verilog hdl quartus uart fpga

ibm / hdl-tools
hdl,Facilitates building open source tools for working with hardware description languages (HDLs)
Organization: ibm
rtl hdl verilog verilator gtkwave

im-tomu / fomu-workshop
hdl,Support files for participating in a Fomu workshop
Organization: im-tomu
Home Page: https://workshop.fomu.im
fomu fomu-workshop vhdl verilog litex fpga riscv hdl chisel migen

intel / rohd
hdl,The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
Organization: intel
Home Page: https://intel.github.io/rohd-website
hardware verification hdl simulator framework hardware-design hardware-verification rtl

kactus2 / kactus2dev
hdl,Kactus2 is a graphical EDA tool based on the IP-XACT standard.
Organization: kactus2
Home Page: https://research.tuni.fi/system-on-chip/tools/
ip-xact eda reuse mpsoc design system-on-chip hardware hdl fpga

kevinpt / symbolator
hdl,HDL symbol generator
User: kevinpt
Home Page: https://kevinpt.github.io/symbolator
hdl vhdl verilog symbol

kitware / veloview
hdl,VeloView performs real-time visualization and easy processing of live captured 3D LiDAR data from Velodyne sensors (Alpha Prime™, Puck™, Ultra Puck™, Puck Hi-Res™, Alpha Puck™, Puck LITE™, HDL-32, HDL-64E). Runs on Windows, Linux and MacOS. This repository is a mirror of https://gitlab.kitware.com/LidarView/VeloView-Velodyne.
Organization: kitware
Home Page: http://www.paraview.org/VeloView/
lidar lidar-camera-calibration lidar-data-manipulation lidar-measurements hdl velodyne-hdl-sensors velodyne velodyne-sensor sensor-streaming sensor-data

langhuihui / monibuca
hdl,🧩 Monibuca is a Modularized, Extensible framework for building Streaming Server
User: langhuihui
Home Page: https://m7s.live
livestream mediaserver hls webrtc rtmp rtsp hdl websocket flv rtp

m-labs / nmigen
hdl,A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
Organization: m-labs
Home Page: https://nmigen.org
fpga hdl yosys nmigen

masc-ucsc / livehd
hdl,Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
Organization: masc-ucsc
asic fpga hdl lgraph live simulation synthesis

mciepluc / cocotb-coverage
hdl,Functional Coverage and Constrained Randomization Extensions for Cocotb
User: mciepluc
cocotb hdl mdv verification

nuand / bladerf-wiphy
hdl,bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
Organization: nuand
bladerf vhdl hdl rtl ofdm ofdm-wireless-communications dsss 80211

pconst167 / sol-1
hdl,Sol-1: A CPU/Computer System made from 74 series logic.
User: pconst167
Home Page: http://sol-1.org
assembler assembly c-compiler cpu electronics hdl operating-system unix verilog

pymtl / pymtl3
hdl,Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
Organization: pymtl
cycle-level-modeling hardware-generation hdl multi-level-modeling open-source-eda open-source-hardware pymtl python rtl systemverilog verilog

raczben / fliplot
hdl,HTML & Js based VCD viewer
User: raczben
Home Page: http://raczben.pythonanywhere.com/
hdl simulation vcd verilog vhdl waveform waveform-viewer

slaclab / surf
hdl,A huge VHDL library for FPGA development
Organization: slaclab
asic firmware fpga hdl python vhdl

spamegg1 / reviews
hdl,Reviewing some online CS courses I took
User: spamegg1
programming-languages algorithms computer-graphics databases logic mathematics networking operating-systems assembly hdl

steffenreith / j1sc
hdl,A reimplementation of a tiny stack CPU
User: steffenreith
fpga spinalhdl forth cpu vhdl verilog hdl j1-cpu

suoto / hdl_checker
hdl,Repurposing existing HDL tools to help writing better code
User: suoto
coc-nvim emacs-lsp ghdl hdl hdl-checker language-server lsp-server mentor-msim modelsim python questasim syntax-checker systemverilog verilog vhdl vim vim-ale vivado-simulator xilinx xilinx-vivado

symbiflow / sphinxcontrib-hdl-diagrams
hdl,Sphinx Extension which generates various types of diagrams from Verilog code.
Organization: symbiflow
Home Page: https://sphinxcontrib-hdl-diagrams.rtfd.io
sphinx sphinx-extension verilog fpga documentation-tool documentation yosys diagrams rtl hdl

tensil-ai / tensil
hdl,Open source machine learning accelerators
Organization: tensil-ai
Home Page: https://www.tensil.ai
machine-learning silicon fpga artificial-intelligence asic hdl scala

trcwm / speech256
hdl,An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.
User: trcwm
Home Page: http://www.moseleyinstruments.com
speech synthesizer fpga hdl verilog retrochallenge

tymonx / logic
hdl,CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
User: tymonx
verilog systemverilog hdl systemc uvm cpp cmake modelsim verilator verification

viduraakalanka / hdl-bits-solutions
hdl,This is a repository containing solutions to the problem statements given in HDL Bits website.
User: viduraakalanka
verilog hdl

wangxuan95 / bsv_tutorial_cn
hdl,一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
User: wangxuan95
Home Page: https://gitee.com/wangxuan95/BSV_Tutorial_cn
bluespec bsv bluespec-systemverilog fpga verilog hardware-description-language hdl

wilsonchen003 / hdlgen
hdl,HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
User: wilsonchen003
automation hdl perl python script verilog asic soc rtl

yupferris / kaze
hdl,An HDL embedded in Rust.
User: yupferris
hdl digital-logic-design rust