Topic: vlsi Goto Github

👇 Here are 249 public repositories matching this topic...

ahirsharan / 32-bit-floating-point-adder
vlsi,Verilog Implementation of 32-bit Floating Point Adder
User: ahirsharan
vlsi xilinx verilog

ahmed-agiza / edaviewer
vlsi,EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
User: ahmed-agiza
Home Page: https://edaviewer.com
webgl serverless hardware viewer eda server-side-rendering serverless-side-rendering cgo pixijs hardware-design

akashtailor-exe / 30-days-of-verilog
vlsi,30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!
User: akashtailor-exe
30-days-of-code 30daysofcode digital-logic-design digitalcircuit verilog verilog-project vlsi rtl-coding rtl-design verilog-programs

andrsmllr / magic_vlsi_examples
vlsi,Some simple examples for the Magic VLSI physical chip layout tool.
User: andrsmllr
vlsi vlsi-physical-design asic

angelojacobo / openlane-sky130-physical-design-workshop
vlsi,Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
User: angelojacobo
asic openlane openlane-flow sky130 vlsi vlsi-physical-design rtl2gds

antonblanchard / vlsiffra
vlsi,Create fast and efficient standard cell based adders, multipliers and multiply-adders.
User: antonblanchard
amaranth-hdl booth dadda physical-design verilog vlsi adder multiplier

arm-university / vlsi-fundamentals-education-kit
vlsi,Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor
Organization: arm-university
microprocessor-implementation cadence-virtuoso synopsys-design arm computer-engineering electrical-engineering hardware-designs vlsi devices-circuits-materials

asinghani / sky130-chip-vis
vlsi,Gate-level visualization generator for SKY130-based chip designs.
User: asinghani
openlane visualization vlsi

asyncvlsi / act
vlsi,ACT hardware description language and core tools.
Organization: asyncvlsi
Home Page: http://avlsi.csl.yale.edu/act
hardware-description-language asynchronous-vlsi eda vlsi-cad asynchronous-circuits cad hdl circuit-simulator design-automation vlsi

asyncvlsi / actflow
vlsi,Top-level repository for the ACT EDA flow
Organization: asyncvlsi
Home Page: https://avlsi.csl.yale.edu/act/
act cad eda vlsi asynchronous asynchronous-circuits asynchronous-vlsi self-timed

asyncvlsi / amc
vlsi,AMC: Asynchronous Memory Compiler
Organization: asyncvlsi
Home Page: http://avlsi.csl.yale.edu/act/doku.php?id=amc:start
eda asynchronous-sram asynchronous-vlsi design-automation vlsi

aucohl / dffram
vlsi,Standard Cell Library based Memory Compiler using FF/Latch cells
Organization: aucohl
verilog vlsi vlsi-physical-design vlsi-circuits electronics-design asic-design

aucohl / ogre
vlsi,Global Router Built for ICCAD Contest 2019
Organization: aucohl
lef-def-parser lef router vlsi asic

briansune / delta-sigma-dac-verilog
vlsi,Delta Sigma DAC FPGA
User: briansune
Home Page: https://briansune.github.io/Delta-Sigma-DAC-Verilog/
dac delta-sigma fpga verilog vlsi

codeshaa / 16-bit-hdlc-using-vhdl
vlsi,High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.
User: codeshaa
hdlc vhdl vlsi

colepoirier / doug
vlsi,Doug is a WIP semi-automated to full manual VLSI Analog and Mixed Signal CAD design tool built with Bevy and Layout21
User: colepoirier
2d bevy cad rust vlsi

cuhk-eda / xplace
vlsi,Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization
Organization: cuhk-eda
eda physical-design placement routability-driven gpu gpu-acceleration vlsi

danchitnis / eesim
vlsi,A browser-based SPICE circuit simulator
User: danchitnis
Home Page: https://EEsim.dev
electronics circuit simulation spice wasm cmos ngspice webassembly emscripten webgl-plot

degatecommunity / degate
vlsi,A modern and open-source cross-platform software for chips reverse engineering.
Organization: degatecommunity
Home Page: https://www.degate.org
verilog vlsi vhdl gui reverse-engineering security security-tools cybersecurity multi-platform chips

efabless / openlane2
vlsi,The next generation of OpenLane, rewritten from scratch with a modular architecture
Organization: efabless
Home Page: https://openlane2.readthedocs.io/
asic drc eda flows gdsii gf180mcu lvs openlane openroad pdk

hsluoyz / atalanta
vlsi,Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
User: hsluoyz
atalanta verilog vlsi atpg

idoka / asic-pinout-drawer
vlsi,Simple pin assignment generator for IC case
User: idoka
Home Page: http://idoka.ru/php-asic-pinout-generator/
asic fpga asciidoc technical-documentation reference-manual datasheet svg pinout vlsi

idoka / mastering-fpgasic-book
vlsi,:book: Mastering FPGASIC Book
User: idoka
fpga asic vlsi book verilog vhdl xilinx altera intel synopsys

ieee-ceda-datc / rdf-2019
vlsi,DATC RDF
Organization: ieee-ceda-datc
vlsi vlsi-physical-design eda vlsi-cad ieee-ceda ieee-ceda-datc design-flow vlsi-design-flow cad design-automation

imsanjoykb / electrical-and-electronic-engineering-course-materials
vlsi,Electrical And Electronic Engineering Course Materials
User: imsanjoykb
Home Page: https://imsanjoykb.github.io/
electrical-engineering electronics-engineering power-system control-systems-engineering biomedical-engineering solid-state-device vlsi vlsi-course fabrication eee-semester-course

jinwookjungs / lefdef_util
vlsi,A LEF/DEF Utility.
User: jinwookjungs
vlsi vlsi-physical-design lef def-parser def placement vlsi-placement bookshelf lef-parser datc-rdf

levibyte / channel_router
vlsi,demo on simple channel router
User: levibyte
vlsi eda routing routing-engine routing-algorithm channel-router

limbo018 / dreamplace
vlsi,Deep learning toolkit-enabled VLSI placement
User: limbo018
vlsi-physical-design deep-learning pytorch vlsi vlsi-placement gpu-acceleration

luckyrantanplan / nthu-route
vlsi,VLSI EDA Global Router
User: luckyrantanplan
Home Page: http://www.cs.nthu.edu.tw/~tcwang/nthuroute/
vlsi vlsi-physical-design vlsi-circuits router eda globalrouter electronic-design-automation ispd lattice-graph multi-maze-routing

mediaic / crash_course_for_new_members
vlsi,Deep Learning & VLSI Crash Course for New Members
Organization: mediaic
deep-learning opencv python pytorch systemverilog verilog vlsi

mihir8181 / vlsi-design-digital-system
vlsi,This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details
User: mihir8181
vlsi digital logic-gates vlsi-designing simulation vlsi-circuits cadence-virtuoso vlsi-project vlsi-design 1bitfulladder

mm-project / qt_painter
vlsi,CAD framework tool on top of Qt
Organization: mm-project
eda cad vlsi qt5 framework design-patterns cpp

nitram2342 / degate
vlsi,Open source software for chip reverse engineering.
User: nitram2342
Home Page: http://www.degate.org/
chip vlsi verilog vhdl visualization gui library image-processing image-recognition reverse-engineering

ntu-lads-ii / fan_atpg
vlsi,FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
Organization: ntu-lads-ii
atpg eda cpp verilog stuck-at vlsi cli lex yacc fan-out

opentimer / opentimer
vlsi,A High-performance Timing Analysis Tool for VLSI Systems
Organization: opentimer
static-timing-analysis sta vlsi vlsi-circuits vlsi-physical-design cpp17 parallel-computing circuit-simulator verilog electronic-design-automation

opentimer / parser-spef
vlsi,A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
Organization: opentimer
static-timing-analysis cpp17 computer-aided-design electronic-design-automation eda sta parasitic spef vlsi vlsi-physical-design

phoenix-digital-design / phoenix
vlsi,phoeniX RISC-V Processor
Organization: phoenix-digital-design
approximate-computing computer-architecture cpu cpu-design embedded-systems fpga microprocessor risc-v riscv vlsi

purdue-onchip / gds2para
vlsi,GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
Organization: purdue-onchip
gdsii parse eda electronic-design-automation vlsi vlsi-circuits integrated-circuits spef interconnect

srohit0 / mida
vlsi,Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"
User: srohit0
Home Page: http://amzn.to/2paZ53b
machine-learning machine-learning-algorithms neural-network machine-intelligence artificial-intelligence artificial-neural-networks feedforward-neural-network logistic-regression polynomial-regression vlsi-circuits

subzer0811 / vlsi
vlsi,All the projects and assignments done as part of VLSI course.
User: subzer0811
recursive-doubling-cla cmos vlsi-circuits vlsi magic ripple-carry-adder universal-shift-register wallace-tree-multiplier verilog

suntrakanesh / system-verilog-bootcamp
vlsi,System Verilog BootCamp
User: suntrakanesh
systemverilog vhdl vlsi ovm uvm verification testbench

synogate / gatery
vlsi,Gatery, a library for circuit design.
Organization: synogate
Home Page: https://www.synogate.com/gatery.html
rtl rtl-design vlsi vlsi-design gatery asic fpga cpp library

tharunchitipolu / dadda-multiplier-using-csa
vlsi,Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
User: tharunchitipolu
verilog dadda-tree vlsi vlsi-project vlsi-design multiplier hardware-description-language fulladder carry-save-adder dadda-multiplier

the-openroad-project / openlane
vlsi,OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Organization: the-openroad-project
Home Page: https://openlane.readthedocs.io/
asic 130nm magic netgen yosys openroad skywater openram vlsi system-on-chip

tinytapeout / xschem-viewer
vlsi,Online viewer of Xschem schematic files
Organization: tinytapeout
Home Page: https://xschem-viewer.com/
analog-design eda schematic vlsi xschem

twweeb / vlsi-physical-design-automation
vlsi,Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
User: twweeb
physical-design-automation vlsi-physical-design vlsi vlsi-cad vlsi-placement vlsi-floorplan vlsi-design vlsi-routing two-way-min-cut fixed-outline

ucdrstdenis / cdsasync
vlsi,cdsAsync: An Asynchronous VLSI Toolset & Schematic Library
User: ucdrstdenis
Home Page: https://ucdrstdenis.github.io/cdsAsync
asynchronous asynchronous-circuits qdi schematic schematic-library verilog ocean skill automated-measurement pvt-sweep

varunnagpaal / digital-hardware-modelling
vlsi,Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
User: varunnagpaal
vhdl systemverilog vlsi hls rtl systemc digital-hardware hardware-models fpga digital-systems

vlsi-eda / poc
vlsi,IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
Organization: vlsi-eda
Home Page: https://tu-dresden.de/ing/informatik/ti/vlsi
vhdl poc-library python simulation synthesis verification vlsi testbenches hardware-modules fpga

yosyshq / padring
vlsi,A padring generator for ASICs
Organization: yosyshq
asic chip eda vlsi yosys