Topic: verilog-project Goto Github

👇 Here are 198 public repositories matching this topic...

7entropy7 / artix_7
verilog-project,My experiments with Nexys4 DDR Artix-7 FPGA Board
User: 7entropy7
fpga-programming verilog nexys4ddr artix-7 verilog-project

adibis / ddr2_controller
verilog-project,DDR2 memory controller written in Verilog
User: adibis
verilog verilog-project ddr hdl

adibis / interrupt_controller
verilog-project,An 8 input interrupt controller written in Verilog.
User: adibis
hdl verilog verilog-components verilog-project

aekanshd / booths-multiplier-using-verilog
verilog-project,
User: aekanshd
verilog verilog-project booths-algorithm

akashtailor-exe / 30-days-of-verilog
verilog-project,30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!
User: akashtailor-exe
30-days-of-code 30daysofcode digital-logic-design digitalcircuit verilog verilog-project vlsi rtl-coding rtl-design verilog-programs

anand270294 / aes-encryption-vsli
verilog-project,EE4415 Project : AES Verilog
User: anand270294
verilog-project digital-design

arjun-narula / traffic-light-controller-using-verilog
verilog-project,the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
User: arjun-narula
verilog verilog-hdl verilog-project verilog-code verilog-programs verilog-simulator vivado vivado-hls vivado-simulator traffic

ashishrana160796 / verilog-starter-tutorials
verilog-project,Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
User: ashishrana160796
hdl verilog circuit switches iverilog verilog-hdl up-for-grabs beginner-friendly logic-gates practice

coole198669 / viterbi_decoder
verilog-project,Hardware Viterbi Decoder in verilog
User: coole198669
verilog-project viterbi-decoder

cw1997 / sdram-controller
verilog-project,SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol
User: cw1997
sdram sdram-controller verilog-project systemverilog hardware hardware-designs

djzenma / 2-fpgas-uart-protocol
verilog-project,Transmitter and Receiver FPGAs connected using the UART Protocol to execute arithmetic operations and display the inputs on the transmitter's 7 Segment Display as well as the result on the Receiver's 7 Segments Display.
User: djzenma
fpga hardware-designs uart-protocol verilog verilog-project

ehsanshahbazii / digital-vlsi-system-design-projects
verilog-project,سورس کد پروژه های درس طراحی سیستم های دیجیتال برنامه پذیر دانشگاه تبریز مقطع کارشناسی رشته مهندسی کامپیوتر
User: ehsanshahbazii
verilog verilog-code verilog-components verilog-project vlsi

emrealci / fpga-verilog
verilog-project,Practices related to the fundamental level of the programming language Verilog.
User: emrealci
comparator fpga frequency-divider hardware-designs hdl latch multiplexer sr-latch verilog verilog-components

flasonil / serial-multiplier
verilog-project,16 bit serial multiplier in SystemVerilog
User: flasonil
verilog verilog-project systemverilog system-verilog

gowtham1729 / image-processing
verilog-project,Image Processing Toolbox in Verilog using Basys3 FPGA
User: gowtham1729
verilog verilog-hdl verilog-project vhdl python3 basys3 basys-board basys fpga pixel

jiachen-meng / verilog-smart-park
verilog-project,This is the final project of Digital Systems Fall 2019@ University of Toronto
User: jiachen-meng
verilog-project

lorentsinani / 16bitcpu-verilog
verilog-project,16 bit CPU created in Vivado with Verilog
User: lorentsinani
computer-architecture verilog verilog-project

luk3sky / building-a-processor---project
verilog-project,Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic
User: luk3sky
verilog-hdl verilog-project processor-architecture hdl alu

lutingwang / fpga
verilog-project,BUAA Computer Organization Project8 FPGA
User: lutingwang
fpga computer-architecture mips32cpu verilog-project

maorassayag / computer-engineering-projects
verilog-project,Digital computer structure, Hardware Design Lab & Introduction to Computers for computer engineering projects in C, C#, Assembly, Pspice.
User: maorassayag
c csharp visual-studio codewarrior controller comunication autonomous-vehicles application-design communication pspice

michaelehab / aes-verilog
verilog-project,Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
User: michaelehab
aes aes-128 aes-192 aes-256 aes-decryption aes-encryption cryptography fpga fpga-board fpga-soc rtl verilog verilog-hdl verilog-project encryption encryption-decryption security learn

mihir8181 / veriloghdl-codes
verilog-project,Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.
User: mihir8181
verilog verilog-project verilog-code verilog-programs verilog-hdl n-bit-alu counter fsm moore-machine-code mealy-machine-code

mnmhdanas / da-based-lms-adaptive-filter
verilog-project,Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be effectively used to implement FIR, IIR and FFT type.The DA logic replaces the MAC operation of convolution summation o into a bit-serial look-up table read and addition operation .
User: mnmhdanas
digital-design lms-algorithm adaptive-filter fir-filter verilog-project verilog distributed-arithmetic

mnmhdanas / uart-protocol
verilog-project,UART - RTL Design and Verification
User: mnmhdanas
digital-design vlsi-design verilog-project verilog uart uart-protocol fpga-programming

mongrelgem / verilog-adders
verilog-project,Implementing Different Adder Structures in Verilog
User: mongrelgem
adder verilog verilog-project verilog-hdl hardware-designs

neelkshah / mips-processor
verilog-project,5-stage pipelined 32-bit MIPS microprocessor in Verilog
User: neelkshah
computer-architecture computer-organization computer-organisation microprocessor microprocessors bits-pilani verilog verilog-hdl verilog-project verilog-programs

nidhinchandran47 / my_rtl_code
verilog-project,Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog
User: nidhinchandran47
hdl rtl-coding verilog verilog-hdl verilog-programs verilog-project vlsi fpga system-verilog vhdl

nikhilmukraj / spiking-neural-networks-hardware
verilog-project,An FPGA design for simulating biological neurons
User: nikhilmukraj
biological-neurons fpga-accelerator izhikevich-neurons neural-network systemverilog-hdl verilog-project computational-biology

pa-tiq / vending_machine
verilog-project,
User: pa-tiq
fpga de10-lite de10nano de10-nano quartus-prime quartus quartus-18-1 verilog verilog-project

pendkeomkar / spi
verilog-project,Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Both SPI and I2C are robust, stable communication protocols that are widely used in today's complex systems.The I2C bus has a minimum pin count requirement and therefore a smaller footprint on the board. The SPI bus provides a synchronized serial link with performance in MHz range.The project implements the bridge between the two protocols and serves as an interface between these two which allow direct communication and a solution to reduce development time and cost for complex embedded systems.
User: pendkeomkar
verilog uvm verilog-hdl verilog-programs verilog-project verification verification-methodologies verification-codes verification-component spi

powerplayer9 / voice-based-motor-control
verilog-project,A verilog HDL based project to control a servomotor with voice commands from an android phone.
User: powerplayer9
verilog-project verilog-hdl servo-motor quartus de10-nano bluetooth terasic-rfs motor-controller voice-commands

prajwalgekkouga / ahb-to-apb-bridge
verilog-project,The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.
User: prajwalgekkouga
ahb amba apb digital fpga modelsim verilog verilog-project

pratikbhuran / voting_machine
verilog-project,Voting machine implemented in verilog
User: pratikbhuran
verilog-hdl verilog verilog-project verilog-code voting-machine voting-system

rpg-7 / hga101_gpu
verilog-project,
User: rpg-7
gpgpu soc-suite verilog-project

sarthak268 / embedded_logic_and_design
verilog-project,This repository contains all labs done as a part of the Embedded Logic and Design course.
User: sarthak268
verilog verilog-hdl verilog-programs verilog-project embedded-systems embedded-logic logic-circuit logic-programming embedded-c c

snbk001 / verilog-design-examples
verilog-project,Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier
User: snbk001
verilog testbenches verilog-design verilog-code verilog-hdl verilog-programs verilog-project self-checking

sudhamshu091 / 32-verilog-mini-projects
verilog-project,Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM
User: sudhamshu091
verilog verilog-project miniproject verilog-hdl

sudhamshu091 / risc-pipelined-processor-32-bit-verilog
verilog-project,Simple Pipelined 32 bit RISC Processor
User: sudhamshu091
pipeline-risc risc-v risc verilog verilog-project verilog-processor

sudhamshu091 / single-cycle-risc-pipelined-processor-verilog
verilog-project,Single Cycle MIPS Pipelined Processor using Verilog
User: sudhamshu091
verilog risc-processor pipelined-risc risc verilog-project

sudhamshu091 / single-cycle-risc-processor-32-bit-verilog
verilog-project,Single Cycle RISC MIPS Processor
User: sudhamshu091
verilog risc-processor verilog-project risc-v risc

tarlaun / cordic
verilog-project,Digital System Design Project - Spring 2020
User: tarlaun
cordic cordic-algorithm verilog-project xilinx-ise

tatan432 / aes_encoder
verilog-project,RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.
User: tatan432
aes-encryption aes-128 encription rtl verilog-project digital digital-design ee4415 synthesis synopsys-dc

thesupercd / 8bit_microcomputer_verilog
verilog-project,This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.
User: thesupercd
verilog verilog-hdl verilog-project verilog-code iverilog 8bit ben-eater ben-eaters-cpu

tongplw / undertale-verilog
verilog-project,👻 Simple Undertale-like game on Basys3 FPGA written in Verilog
User: tongplw
undertale basys3 basys3-fpga verilog verilog-project fpga fpga-game fpga-board vga uart

ultraembedded / minispartan6-audio
verilog-project,miniSpartan6+ (Spartan6) FPGA based MP3 Player
User: ultraembedded
mp3player fpga risc-v spartan6 verilog verilog-project audio sd-card rv32im

vasanthkumar18 / cache-compression
verilog-project,Cache compression using BASE-DELTA-IMMEDIATE process in verilog
User: vasanthkumar18
cache cache-compression bdi-model project verilog-project verilog-code hardware-project hacktoberfest hacktoberfest2021

vedic-partap / computer-organization-and-architecture-lab
verilog-project,Solution to COA LAB Assgn, IIT Kharagpur
User: vedic-partap
coa hardware-designs verilog-project verilog cpu mips-assembly

vsasakiv / rv32i_processor
verilog-project,Risc-V 32i processor written in the Verilog HDL
User: vsasakiv
risc-v riscv32 riscv32i verilog verilog-code verilog-hdl verilog-project

xiazhuo / nscc2022_personal
verilog-project,NSCSCC2022龙芯杯个人赛，MIPS32，59MHz经典五级流水线架构，易于初学者阅读（计算机组成原理，自己动手写CPU）
User: xiazhuo
mips32 nscscc2022-single verilog-project

zslwyuan / basic-simd-processor-verilog-tutorial
verilog-project,Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
User: zslwyuan
simd processor verilog processor-design verilog-project multiplier adder instruction-set-architecture cadence-virtuoso cpu