snbk001 / verilog-design-examples

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier

Verilog-Design-Examples

• Use Verilog/System Verilog for design
• Always write a Testbench for a design
• Testbench should be self-checking test bench
• Testbench should use task for sending input data to the DUT

Verilog Designs with Testbenches

1. Half Adder
2. 1-bit Full Adder
3. 1-bit Full Adder using Half Adder
4. 4-bit full adder using Half Adder
5. Mux using Case statement
6. Mux using with the use logical expression
7. Mux using Conditional operator
8. ALU
9. D Flip Flop with synchronous reset
10. D Flip Flop with asynchronous reset
11. Sequence Detector using Mealy machine (1101, Non-Overlapping)
12. Sequence Detector using Moore machine (1101, Non-Overlapping)
13. Sequence Detector using Mealy machine (1101, Overlapping)
14. Sequence Detector using Moore machine (1101, Overlapping)
15. Count the Number of 1s
16. Binary to Gray Conversion
17. Up Down Counter
18. Random Counter
19. Clock Divider
20. PIPO
21. n bit universal shift register
22. 4 bit LFSR
23. Custom Design
24. Single port RAM (128x8)
25. Dual port RAM (128x8)
26. Synchronous FIFO
27. Asynchronous FIFO
28. 8x8 Sequential Multiplier
29. 64 bit Pipelined Multiplier