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00-ihp-open-pdk

130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design

00-openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

100-days-of-ml-code

100-Days-Of-ML-Code中文版

2dconv-fpga

A 2D convolution hardware implementation written in Verilog

32-verilog-mini-projects

Implementing 32 Verilog Mini Projects

addernet

Code for paper " AdderNet: Do We Really Need Multiplications in Deep Learning?"

arm_amba_design

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

atomfpu

IEEE-754 Single Precision Floating Point Unit

awesome-matlab-robotics

This is a list of awesome demos, tutorials, utilities and overall resources for the robotics community that use MATLAB and Simulink.

basic_verilog

Must-have verilog systemverilog modules

blog-codes

个人博客 (https://fancyerii.github.io/) 文章的代码

cgra_x_heep

Low-power CGRA architecture for embedded systems

chisel-bootcamp

Generator Bootcamp Material: Learn Chisel the Right Way

chisel3

Chisel 3: A Modern Hardware Design Language

cnn-fpga

Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database

cnn-on-fpga

FPGA

convolution

using verilog and vivado to implement convolution

core_sdram_axi4

SDRAM controller with AXI4 interface

etiss

Extendable Translating Instruction Set Simulator

fpga-fixedpoint

A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

fpga-proj

FPGA project

fpu

IEEE 754 floating point unit in Verilog

graphxai

GraphXAI: Resource to support the development and evaluation of GNN explainers

gym-eplus

hardware-multiplier-architectures

Verilog implementations of 6 different hardware multiplier architectures

hdl-bits-solutions

This is a repository containing solutions to the problem statements given in HDL Bits website.

ibm_capstone_proj

IBM_couesera

ieee-convert

A simple routine in Verilog HDL that converts integers into IEEE 754 Floating Point format.

ml-university

Machine Learning Open Source University

open-nic

AMD OpenNIC Project Overview