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16.0 6.0 8.0 39.86 MB

License: GNU General Public License v3.0

Perl 0.04% SystemVerilog 8.17% C 6.91% Verilog 81.33% HTML 1.52% Makefile 0.04% Shell 0.72% Stata 0.15% Tcl 0.01% C++ 0.98% PHP 0.05% NASL 0.07% SourcePawn 0.01% Assembly 0.01% Pascal 0.01%
gpgpu soc-suite verilog-project

hga101_gpu's Introduction

HGA101 is a crude GPGPUdesign, with a 5-stage RISC-V32ia core and a 16bit*8lane integer/half-precision float SIMD pipeline.

this is a part of the RV-AT project (https://github.com/RV-AT)

Now everything is WIP

Please bare this in mind: THIS IS AN EXPERIMENTAL DESIGN AND I DO NOT PROVIDE ANY GUARANTEE

Some more info and thank will be added here after FPGAChina 2020 competetion finished, and I will keep working on this project

Now status:

Code Core done, SoC Not started

Testbench Module level TB WIP , Core TB not started

Hardware Not started

Scripts Test and elaborate suite WIP

hga101_gpu's People

Contributors

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Forkers

rv-at mfkiwl benjamin-underwood arryboom rainscut orb1t-ua cxlisme

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