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nidhinchandran47 Goto Github PK

followers: 12.0 following: 32.0 repos: 15.0 gists: 0.0

Name: Nidhin Chandran

Type: User

Company: Cochin University of Science and Technology

Bio: もう一人で歩くことはありませんよ 59 6f 75 27 6c 6c 20 4e 65 76 65 72 20 57 61 6c 6b 20 41 6c 6f 6e 65

Twitter: nidhin_47

Location: Kochi

Welcome to my GitHub!

Tip

👀 I’m interested in Front-end VLSI Design
🌱 I’m currently learning System Verilog and UVM.
💞️ I’m looking for moments of peace
⚡ Fun Fact : "I'm always there, front and center, for every Liverpool game." #YNWA

🏄🏼‍♀️protfolio

📫 How to reach me?	🔗 My Free-time Crafts (Build with )	🎯 I'm Currently Buzy with
Note 📧 Email Twitter LinkedIn	Warning 📝 LaTeX Cheat Sheet VIM Cheat Sheet 🔦 Digital Electronics Notes	Caution 🤖 DV200 👾 HDL Bits Solutions

Nidhin Chandran's Projects

4-bit-alu

This is the verilog code for a 4bit arithmetic and logic unit which can do 8 operations

circuitverse-interactive-book

Interactive Online Book on Digital Logic Design

dv200

A go-to repository for exploring, learning, and mastering RTL design and verification.

ev-high-efficiency-boost-converter

This is a high-efficiency boost converter designed for quicker charging of electric vehicles.Prototype 1.

flotadder

This is the VHDL code for a floating point adder

The HDL Bits Solutions repository provides answers to the HDL Bits exercises, which are designed for practicing digital hardware design using Verilog HDL. Join us to learn, share, and master digital design!

mac_unit

This is a 4 bit MAC unit ,which is the basic unit of matric multiplier used in TPU

markdown-cheatsheet

Markdown Cheatsheet for Github Readme.md

mips32

Verilog implementation of a mips32 processor

mips_testbench_generator

A MIPS based microprocessor and a python script for automatic generation of testbench corresponding to the input assembly file

my_rtl_code

Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog