Topic: vivado-hls Goto Github
Some thing interesting about vivado-hls
Some thing interesting about vivado-hls
vivado-hls,Designing local adaptive thresholding using integral images from scratch. "Efficient Implementation of Local Adaptive Thresholding Techniques Using Integral Images" by Faisal Shafait, Daniel Keysers, Thomas M. Breuel was used as guideline.
User: abdullahashfaq
vivado-hls,the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
User: arjun-narula
vivado-hls,A Vivado HLS Command Line Helper Tool
User: benjmarshall
vivado-hls,This implementation of RSA is on an FPGA platform to test the performance of the algorithm in terms of latency as a comparison to AES
User: bharathsharma95
vivado-hls,Introduction in Reconfigurable Computing (using reconfigurable Systems-on-Chip rSoC)
User: cspyridakis
vivado-hls,A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
User: definelicht
vivado-hls,Simple tutorials for getting started with programming on Trenz ArduZynq boards.
User: duartegalvao
vivado-hls,Machine learning on FPGAs using HLS
Organization: fastmachinelearning
Home Page: https://fastmachinelearning.org/hls4ml
vivado-hls,Lenet for MNIST handwritten digit recognition using Vivado hls tool
User: floyedshen
vivado-hls,Advanced Computer Architecture at EPFL.
User: frblazquez
vivado-hls,a library of DART-enabled hw IPs
Organization: fred-framework
vivado-hls,This framework was part of the Diploma thesis titled "Architectures and Implementations of the Neural Network LeNet-5 in FPGAs". The main goal of this thesis was to create a LeNet-5 implementation in an FPGA development board, but also form a reusable framework/workflow which can be modified to model and develop other Neural Networks as well.
User: georgevangelou
vivado-hls,The second place winner for DAC-SDC 2020
User: jiangwx
vivado-hls,HLS & hls4ml Tutorial
User: jmduarte
Home Page: https://fastmachinelearning.org/
vivado-hls,running ANN on an FPGA
User: jochist
vivado-hls,Source codes for High Level Synthesis for Fixed Progammable Gate Arrays (FPGAs). Can be converted to RTL using Vivado HLS or SDSoC.
User: joshuaebenezer
vivado-hls,University of Pittsburgh ECE 1195
User: jtp75
vivado-hls,MNIST accelerator using pynq-z2 and the binary qunatization
User: junwha0511
vivado-hls,A Vivado HLS project generator
User: kenta11
vivado-hls,HLS SHA-3 Accelerator
User: khaled-e-a
vivado-hls,Recipe for FPGA cooking
User: lastweek
vivado-hls,[DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
User: licheng-guo
vivado-hls,Multimedia SoC design (2020 Fall)
User: linkingmon
vivado-hls,This project implements a convolution kernel based on vivado HLS on zcu104
User: lirui-shanghaitech
Home Page: https://lirui-shanghaitech.github.io
vivado-hls,Repository of DB4HLS. A database of design space exploration in high-level synthesis.
User: lorenzoferretti
Home Page: https://www.db4hls.inf.usi.ch/
vivado-hls,Reconfigurable Digital Systems HRY591-project.
User: manwlis
vivado-hls,This is an IoT Edge computing system powered by an ANN to predict floods on cities near Mississippi river
User: mavalderrama
vivado-hls,FPGA implementation of Canny edge detection by using Vivado HLS
User: medalotte
vivado-hls,Accelerated Stencil Computation with Optimized Dataflow Architecture on FPGAs
User: miltosmac
vivado-hls,Quick Verilog Module Isolator - Isolates a design for testing.
User: ngiambla
vivado-hls,FPGA Cryptography for High-Level Synthesis
User: petrsocha
vivado-hls,Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..
User: prajjv
vivado-hls,The aim of this project is to demonstrate the working of the RF Data Converter IP by analyzing and replicating a part of the official Xilinx design. The goal is to recreate the radio hierarchy using custom IPs (amplitude controller and packet generator) designed in Vitis HLS 2022.1.
User: riyasach189
vivado-hls,A fast and efficient implementation of a SHA256 cracker
User: sanjay-a-menon
vivado-hls,The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
User: sinakarvandi
Home Page: https://rayanfam.com/topics/hardware-design-stack/
vivado-hls,Huffman encoding core (Vivado HLS Project)
Organization: sopynq
vivado-hls,FPGA acceleration of arbitrary precision floating point computations.
Organization: spcl
vivado-hls,DaCe - Data Centric Parallel Programming
Organization: spcl
Home Page: http://dace.is/fast
vivado-hls,Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
Organization: spcl
vivado-hls,Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
Organization: spcl
vivado-hls,Implementation of the N^2-formulation of N-body simulation with Vivado HLS for SDAccel platforms.
Organization: spcl
vivado-hls,Implementation of time and space-tiled stencil in Vivado HLS.
Organization: spcl
vivado-hls,Inference Design, Behavioral simulations, and Hardware Implementation.
User: thadoe
vivado-hls,CPU implementation of the Image stitching using FAST. For FPGA implementation visit tharaka27-SocStitcher.
User: tharaka27
vivado-hls,[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
Organization: ucla-vast
Home Page: https://tapa.rtfd.io
vivado-hls,SOC of two_stream action recognition on ZCU102
User: wubinary
vivado-hls,Real-time binocular stereo vision FPGA system with OV5640 cameras
User: yangjl-cs
vivado-hls,Real-time binocular stereo vision FPGA system with OV5640 cameras
User: zhutmost
vivado-hls,Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis
User: zslwyuan
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