Topic: zynq-7000 Goto Github
Some thing interesting about zynq-7000
Some thing interesting about zynq-7000
zynq-7000,Sampling and processing of audio data from microphone arrays
Organization: acoustic-warfare
zynq-7000,Simple safe lock mechanism written in SystemVerilog.
User: arokasprz100
zynq-7000,Global Dark Mode for ALL apps on ANY platforms.
User: b1f6c1c4
zynq-7000,FastPath_MP: An FPGA-based multi-path architecture for direct access from FPGA to NVMe SSD
Organization: beehive-lab
zynq-7000,Custom CPU in VHDL, ZedBoard
User: bernigelectronic
zynq-7000,MSc Final Project
User: bernigelectronic
zynq-7000,AD9361 FM Radio Verilog LVDS
User: briansune
Home Page: https://briansune.github.io/AD9361-FM-Radio-Verilog-LVDS/
zynq-7000,Hardware and Software Co-design implementations
User: bselimoglu
zynq-7000,Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
User: dsa-shua
zynq-7000,Simple tutorials for getting started with programming on Trenz ArduZynq boards.
User: duartegalvao
zynq-7000,This repository documents Interfacing HDMI and VGA with Pynq Z2 Board using Vivado block design and RTL.
User: embedded-explorer
zynq-7000,Fully connected dense neural network in SystemVerilog, synthesisable to an FPGA for neural network computation acceleration
User: erwanregy
zynq-7000,FPGA design automation for real-time, dynamic partially reconfigurable application
Organization: fred-framework
zynq-7000,Main repository to install FRED
Organization: fred-framework
zynq-7000,Yocto layer for the FRED framework
Organization: fred-framework
zynq-7000,Simple API for working with AXI DMA on Zynq-7000
User: good-stuff
zynq-7000,Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP
User: hamid-r-tanhaei
zynq-7000,This is 8 channels BISS-C FPGA hardware board design
User: hello-fpga
zynq-7000,This is xc7z020clg400 FPGA hardware core board design
User: hello-fpga
zynq-7000,This repository contains my Linux builds and projects for ZYBO Zynq dev board
User: hossein1387
zynq-7000,Firmware with overclock support for LibreSDR (PlutoSDR clone with Zynq 7020), 27.5 MSPS sample rate over Gigabit Ethernet with libiio/PlutoSDR API
User: hz12opensource
zynq-7000,SpaceVNX (VITA 74.4) carrier based on Zynq-7000.
User: kindam3h
zynq-7000,Real-Time Operating System (RTOS) for Xilinx Zynq-7000 Cortex-A9 (ARMv7-A) multi-core SoCs (ZedBoard, PicoZed, MicroZed and similars) based on the ARINC 653 Part 1 specification
User: lfarcaro
zynq-7000,Integration on PL side of Zynq7000 for PYNQ framework of common industrial devices (GPIO, I2C, SPI and UART)
Organization: makarenalabs
zynq-7000,A script automation project for compiling Xenomai on a Zynq-7000 FPGA
User: mariobarbareschi
zynq-7000,Deep Learning Processing Unit (DPU IP) integration with Application Processing Unit (APU) using (Zynq-7000 PS) in Xilinx Vivado Design Suite
User: mohammadasim98
zynq-7000,Github repo for monius/petalinux in docker hub.
User: mon-ius
Home Page: https://hub.docker.com/r/monius/petalinux
zynq-7000,Implementation of a VGA Controller in Verilog (Both Graphics Mode and Text Mode)
User: narendiran1996
Home Page: https://narendiran1996.github.io/project-blogs/jekyll/update/2020/08/14/vgaController.html
zynq-7000,This repository contains the C code for ARM Implementation of FFT on Zynq-7000 APSoC from Xilinx.
User: neeraj1397
zynq-7000,Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.
User: neeraj1397
zynq-7000,⚙️ 基于 Zynq-7 全可编程 SoC 的设计
User: nekosilverfox
zynq-7000,Projects System On Chip (Zynq700)
User: omaraskour
zynq-7000,A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)
User: snrnothere16
zynq-7000,A ZYNQ 7020 project that plays breakout via HDMI.
User: snrnothere16
zynq-7000,A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample data is displayed using a Graphical User Interface which mimics an Oscilloscope.
User: splacharya
zynq-7000,Yet Another XC7Z010 Board
User: stanlazy
zynq-7000,Shell like program to run on the Zynq while experimenting
User: svenssonjoel
zynq-7000,Dual-Mode PSK Transceiver on SDR With FPGA
User: teddy-van-jerry
Home Page: https://go.wqzhao.org/sdr-psk-fpga
zynq-7000,Try to embed it on Zynq board.
User: vencifreeman
zynq-7000,一个PLadc数据采集,PS以太网lwip接收数据到PC的vivado工程。
User: wataru030-xiaohei
zynq-7000,Hands-On Embedded's Repository
User: yohanes-erwin
Home Page: http://handsonembedded.com
zynq-7000,[Course] Hands-On ZYNQ: Mastering AXI4 Bus Protocol
User: yohanes-erwin
zynq-7000,This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation
User: zslwyuan
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