lastweek / fpga_readings

Recipe for FPGA cooking

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Updates

07/14/2021:

Just a couple thoughts I want to share.

This repo has not been updated for a while. Although I'm still collecting FPGA pages in my own Zotero, I haven't added them here. Also, I no longer use Xilinx HLS as my main development language. I started using Scala-based languages such as SpinalHDL and Chisel (mostly SpinalHDL). I think they are very expressive, practical, and fit the hardware model very well. And they have been used across many successful projects (e.g., Xiangshan, BOOM, etc).

Xilinx HLS still has its place in Industy, at least for now. Google's latest Video Processing Unit (ASPLOS'21) is designed using HLS. They praise for HLS's C++ model, hence able to enjoy a lot language sanity checking. I guess they must have a set of good HLS practices to make it work.

Also, if you are into network-related processing, go checkout the Corundum.io project. In fact, check out all the projects from Alex Forencich. Dude is a lengend in the open-source FPGA world, he is making such a big impact on the whole research community.

FPGA has never been so hot for system researchers. People are using it to build various things, prototyping for ASIC etc. It aids networking, storage, machine learning. With those high-quality open-source RISC-V cores, network stack and so on, sky is the limit.

Everyone is welcomed to contribute. You can add new papers, new code, new practice lessons, and so on.

Cook FPGA

This repository is intended for folks who are new and want to learn something about FPGA. This repository is a collection of useful resources and links rather than a thorough FPGA tutorial. Traditional HDL (Hard and Difficult Language) is not the main focus, instead, we focus on using high-level languages (e.g., C++) to cook FPGA.

Originally, this repository was started by a newbie to record his learning of FPGA, and late made public in the hope that it could help researchers to start their journey along with FPGA, with less pain and whiskey.

Resources collected here, or the way contents are organized, are not in their perfect shape. This repository is still raw and need major improvements. Any form of contribution is welcomed and appreciated.

Main contents:

• README.md
  • Basics about Digital Design
  • Basics about FPGA
  • Relevant Courses and Books
  • Papers about FPGA internal
• Xilinx
  • xilinx.md
  • xilinx_constraints.md
  • xilinx_cheatsheet.md
  • xilinx_lessons_vivado.md
  • xilinx_lessons_hls.md
• submodules/: Github repositories about FPGA
• hls/: Sample Xilinx HLS C++ code
  • AXI Stream
  • Network protocol processing
• xilinx_arty_a7: Sample Xilinx projects for Arty A7 100 board
  • Tri-mode MAC reference design
  • Simple LED
  • Clocked LED
• FAQ.md
  • Some implementation questions about FPGA

Resources

Papers

List of academic papers.

FPGA Intro

• URL: RapidWright FPGA Architecture Basics
• URL: RapidWright Xilinx Architecture Terminology
• Book: Parallel Programming for FPGAs
  • Basic about FPGA and HLS
• URL: All about FPGAs, EE Times
• Slides: Intro FPGA CSE467 UW
• URL: I/O Pads
  • BGA Wiki: In a BGA the pins are replaced by pads on the bottom of the package. If you check PGA package, you will know the difference between pin and pad, and immediately get why it is called pad. And you will also know what's the pad in the IO Block diagram.

Digital Basics

• PDF: The Digital World
• Wiki: Differential signaling and Wiki: Single-ended signaling
  • Paper: Differential Signals The Differential Difference! Douglas Brooks
• Book: Digital design and computer architecture
• Content-Addressable Memory Introduction

Verilog

• Verilog Introduction
• Verilog HDL Quick Reference Card
• Xilinx UG901 Synthesis

High-Level Synthesis (HLS)

• A Survey and Evaluation of FPGA High-Level Synthesis Tools
• Xilinx Introduction to FPGA Design with Vivado High-Level Synthesis
• Xilinx Vivado Design Suite User Guide High-Level Synthesis
• Xilinx SDAccel Development Environment Help for 2018.2 XDF
• The Zynq book
• Parallel Programming for FPGAs
• GMU ECE 699 Software/Hardware Co-design S15
• CMU ECE 18-643
• Cornell ECE5775 from Prof. Zhiru Zhang

Courses

• Online: Real Digital
• CMU ECE 18-643
  • I like its slides, very informative. Slides about PR, Verilog, HLS are good.
  • Also read its references, all quite good papers.
• Cornell ECE5775 from Prof. Zhiru Zhang
• GMU ECE 699 Software/Hardware Co-design S16
• GMU ECE 699 Software/Hardware Co-design S15
  • DAMN, this is a good and practical course.
• MIT 6.111 Introductory Digital Systems Laboratory
• MIT 6.375 Complex Digital Systems
• UCB EECS 151/251A

Books

• Parallel Programming for FPGAs
• The Zynq book
• FPGAs for Software Programmers
• Data Processing on FPGAs, Synthesis Lectures on Data Management

fpga_readings's Issues

TODO: write a doc about how to construct CPU-like pipeline in HLS

Question about organizing the content!

Hi,

This is a really cool repository for two main reasons! First is that I like the incentives regarding learning FPGAs, second, the manner that you have about how you are getting started with this research area.

I was looking at different places to learn more about this area since we can see so many specialized devices for data center applications like programmable NICs, Switches, accelerators for Graph Processing and ... I also really like the paper at OSDI'18 - "Sharing, Protection, and Compatibility for Reconfigurable Fabric with AmorphOS." They have not shared so many details about the implementation stuff unlike your paper there!

Anyway, I would be happy to contribute to this repository. You shared a lot in this repository, however, that would be awesome if you could add a section in the README.md indicating the best order of reading the content there!

The Get Started section is also pretty packed, it is possible to look through all content but it is not time efficient. The RapidWright FPGA Architecture Basics was really good for me! Like there are a couple of courses and you marked one of them as the most practical one, and that would be the one I read first!

TODO: write a doc about how to achieve max mem BW using HLS

Question about choosing the board

Hi,

I was wondering how you chose arty_a7 for the sample projects? Why you didn't choose the zen board?

Thanks