Question about choosing the board about fpga_readings

[lastweek]

Hi @sarsanaee!

We have a specific requirement that Zedboard can not easily provide. We want a flow like this: PHY <-> MAC <-> Customized IP.

With Zedboard, the on-board PHY is connected to the PS part, not the PL part. Maybe there is a solution to route PHY's traffic from PS to PL, but we don't want the trouble (honestly, I gave up initially). Or you buy another daughter board with a PHY.

Arty A7 is a simple normal board, with a 7 serious FPGA chip, and no-board PHY. We can easily have the PHY - MAC - Customized IP flow. I think this is also the model you are interested in?

[lastweek]

Besides, Arty A7 is not expansive, a good entry-level board.

[sarsanaee]

Yeah, that's right. I'm just interested in some similar objectives!

Arty A7 100T should be sufficient thought! Maybe more than sufficient for initial development.

[sarsanaee]

Hi @lastweek

Thank you for the explanation, I have got my answer. I guess Arty A7 should be what I need to consider.

By the way, you might want to elaborate your justifications on this issue in the READMEs if you find it helpful for people.

-Ali

[lastweek]

We can just keep this issue open. It's alright.

I'm assuming you are trying to do similar network related processing, right? The arty board is a good starting board to play with, but it has limited resource. A baseline design that only has MAC, MC, and some simple HLS IP already take ~30% of the LUTs. For a real development, we need some more powerful ones. In fact, we already started looking middle-end fpga boards.

You can find a PoC design of the above PHY <-> MAC <-> Customized IP <-> MC <-> DRAM here: https://github.com/lastweek/FPGA/tree/master/xilinx_arty_a7/pdpm_arty_a7