jiachen-meng / verilog-smart-park

This is the final project of Digital Systems Fall 2019@ University of Toronto

verilog-smart-park

This is the final project of Digital Systems Fall 2019 @ University of Toronto, Faculty of Applied Science & Engineering
This project is a fully-automated parking garage that can accommadate different types of cars in spots of different sizes
For details please read this final report

Authors

Jingyi Chen ([email protected])
Jiachen Meng ([email protected])

Notice

Please do not copy any code from this repository for academic purposes.

Required Material

Intel Quartus Prime
Intel DE1-SoC FPGA board
A VGA display

To run

Open "RamVgaTest.qpf" project file with Quartus
Add "DE1_SoC.qsf" file in the assignment section (this file can be found online from other sources)
Include all other files in the repository
Compile the projecthopefully it's successful :)
Load the compiled project onto the board
ENJOY!