briansune / delta-sigma-dac-verilog

Delta Sigma DAC FPGA

Delta-Sigma-DAC-Verilog

If this project is constructive, welcome to donate a drink to PayPal.

The measurements are conducted on Spartan 7 Xilinx FPGA with LPF setting - (680R, 1nF).

Common questions:

Why it work?

1 bit flip-flop the basic building block of a R-2R DAC hences it is a DAC because it can convert logic to voltage.

Of cause it is just limited to 0 - low voltage, 1 - high voltage.

When it is modulated with a carrier frequency it start to make all senses that it can be a really good DAC.

Why two stages?

The best answer can be referenced from : https://www.beis.de/Elektronik/DeltaSigma/1stOrderDisadvantages.html https://www.youtube.com/embed/4SIJTl5du60?start=1300

In short when 0 or max (-ve, +ve) is insert to the DAC, the output will result in high tone amputitude that can be reduce via 2 stages.

Oscillscope Measure:

Single Stage Delta-Sigma DAC:

Resource on FPGA:

What bitwidth is required on the first stage?

This is commonly considered with i.e. 16bit Input + 2bit.

Two Stage Delta-Sigma DAC:

Resource on FPGA:

There are a major question when designing the ΔΣ DAC:

What bitwidth is required on the second stage?

My approach is considering 1st stage output i.e. [16bit + 2bit] + over_sample_rate (i.e. 2^[6] 6bit).

over_sample_rate for example 2^6 or above

delta-sigma-dac-verilog's Issues

off-topic: UP5K with flex sensor

Hi Brian, a little out of my depth.
I'd like to connect flex sensor to UP5K FPGA which has LVDS
in principal could this work?
any advice, things to look out for?

thanks!!

https://learn.sparkfun.com/tutorials/flex-sensor-hookup-guide

https://www.latticesemi.com/products/designsoftwareandip/intellectualproperty/referencedesigns/referencedesign03/simplesigmadeltaadc

Rationale for increasing 2nd stage accumulator bitwidth with OSR bits?

Hi,

I'm using your DAC as an audio DAC. It's working very well. I do have two questions, however:

What bitwidth is required on the second stage?
My approach is considering 1st stage output i.e. [16bit + 2bit] + over_sample_rate (i.e. 2^[6] 6bit).

What is the rationale for increasing the 2nd stage accumulator bitwidth with OSR bits? Is this documented in literature somewhere?

2. The feedback DAC value is + or - MID_VAL with MID_VAL defined as:
   MID_VAL = 2**(DAC_BW - 1) + 2**(OSR + 2)

2**(DAC_BW - 1) corresponds to the maximum input sample amplitude, so that makes sense, but why the OSR term?

Thanks for any clarification and/or pointers to literature.