off-topic: UP5K with flex sensor about delta-sigma-dac-verilog

[briansune]

@peepo

Welcome~
With humble experience on such resistor based sensor.

First do you want ADC or DAC?
Of cause, if you need ADC then according to my short investigation it could work but really not that good at low and high rail.
While the middle range is kind of okay.

Let me explain why it is problematic.
As we all know development board usually tide the BANK IO to a fixed DCDC. So this means noisy and poor PSSR.
Meanwhile if you really need to interface with analog sensors, the best way is to use additional comparator and LDO supply.
Then interface with FPGA.

Or better solution would be use ADC-equipped FPGA. Otherwise a huge trade-off must be encountered.
As usual there are no free lunch in this world so a cheaper solution means suboptimal performance.

You can always try on FPGA with differential input P-N IO(s).
But the capacitor and resistor trade-off is so touchy.

Additional info is that people think FPGA digital ADC do not impacted by the supply rail, but Dt-Sig for my understanding is that you are mimicking an analog voltage and compare. So how do you measure good analog readings when it is very noisy from beginning? While DAC is another story, because we are using tricks that make perfectly on FPGA speed. All about noise floor and over-sampling.

Unless production cost is ultra-constrained why not add off-shelf ADC via SPI or IIC?
Of cause you might consider additional phy layer, however the Dt-Sig itself also is a kind of PHY layer so no big different to me.

Hope this help =]

ENJOY~