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Home Page: https://briansune.github.io/Delta-Sigma-DAC-Verilog/
License: MIT License
Delta Sigma DAC FPGA
Home Page: https://briansune.github.io/Delta-Sigma-DAC-Verilog/
License: MIT License
Hi Brian, a little out of my depth.
I'd like to connect flex sensor to UP5K FPGA which has LVDS
in principal could this work?
any advice, things to look out for?
thanks!!
https://learn.sparkfun.com/tutorials/flex-sensor-hookup-guide
Hi,
I'm using your DAC as an audio DAC. It's working very well. I do have two questions, however:
What bitwidth is required on the second stage?
My approach is considering 1st stage output i.e. [16bit + 2bit] + over_sample_rate (i.e. 2^[6] 6bit).
What is the rationale for increasing the 2nd stage accumulator bitwidth with OSR bits? Is this documented in literature somewhere?
2**(DAC_BW - 1) corresponds to the maximum input sample amplitude, so that makes sense, but why the OSR term?
Thanks for any clarification and/or pointers to literature.
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