OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Home Page: https://openlane.readthedocs.io/
License: Apache License 2.0
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I'm using Ubuntu (see below) and this system successful build rc2 and ran the example design spm
Distributor ID: Ubuntu
Description: Ubuntu 20.04.1 LTS
Release: 20.04
Codename: focal
The docker build fails on vlogtoverilog
~/git/openlane-develop/docker_build$ make build-vlogtoverilog
mkdir -p logs/docker
export DOCKER_BUILDKIT=1; docker build --rm -t vlogtoverilog docker/vlogtoverilog | tee logs/docker/vlogtoverilog.build.txt
[+] Building 15.3s (5/16)
=> [internal] load build definition from Dockerfile 0.0s
=> => transferring dockerfile: 38B 0.0s
=> [internal] load .dockerignore 0.0s
=> => transferring context: 2B 0.0s
=> [internal] load metadata for docker.io/library/centos:centos6 0.0s
=> CACHED [1/13] FROM docker.io/library/centos:centos6 0.0s
=> ERROR [2/13] RUN yum -y install centos-release-scl && yum -y install devtoolset-6 devtoolset-6-libatomic-devel 15.2s
------
> [2/13] RUN yum -y install centos-release-scl && yum -y install devtoolset-6 devtoolset-6-libatomic-devel:
#5 0.415 Loaded plugins: fastestmirror, ovl
#5 0.622 Setting up Install Process
#5 12.38 Resolving Dependencies
#5 12.38 --> Running transaction check
#5 12.38 ---> Package centos-release-scl.noarch 10:7-4.el6.centos will be installed
#5 12.38 --> Processing Dependency: centos-release-scl-rh for package: 10:centos-release-scl-7-4.el6.centos.noarch
#5 12.48 --> Running transaction check
#5 12.48 ---> Package centos-release-scl-rh.noarch 0:2-4.el6.centos will be installed
#5 12.49 --> Finished Dependency Resolution
#5 12.50
#5 12.50 Dependencies Resolved
#5 12.50
#5 12.50 ================================================================================
#5 12.50 Package Arch Version Repository Size
#5 12.50 ================================================================================
#5 12.50 Installing:
#5 12.50 centos-release-scl noarch 10:7-4.el6.centos extras 12 k
#5 12.50 Installing for dependencies:
#5 12.50 centos-release-scl-rh noarch 2-4.el6.centos extras 12 k
#5 12.50
#5 12.50 Transaction Summary
#5 12.50 ================================================================================
#5 12.50 Install 2 Package(s)
#5 12.50
#5 12.50 Total download size: 24 k
#5 12.50 Installed size: 39 k
#5 12.50 Downloading Packages:
#5 12.78 --------------------------------------------------------------------------------
#5 12.78 Total 85 kB/s | 24 kB 00:00
#5 12.78 warning: rpmts_HdrFromFdno: Header V3 RSA/SHA1 Signature, key ID c105b9de: NOKEY
#5 12.79 Retrieving key from file:///etc/pki/rpm-gpg/RPM-GPG-KEY-CentOS-6
#5 12.81 Importing GPG key 0xC105B9DE:
#5 12.81 Userid : CentOS-6 Key (CentOS 6 Official Signing Key) <[email protected]>
#5 12.81 Package: centos-release-6-10.el6.centos.12.3.x86_64 (@CentOS/6.10)
#5 12.81 From : /etc/pki/rpm-gpg/RPM-GPG-KEY-CentOS-6
#5 12.83 Running rpm_check_debug
#5 12.83 Running Transaction Test
#5 12.84 Transaction Test Succeeded
#5 12.84 Running Transaction
Installing : centos-release-scl-rh-2-4.el6.centos.noarch 1/2
Installing : 10:centos-release-scl-7-4.el6.centos.noarch 2/2
Verifying : centos-release-scl-rh-2-4.el6.centos.noarch 1/2
Verifying : 10:centos-release-scl-7-4.el6.centos.noarch 2/2
#5 13.05
#5 13.05 Installed:
#5 13.05 centos-release-scl.noarch 10:7-4.el6.centos
#5 13.05
#5 13.05 Dependency Installed:
#5 13.05 centos-release-scl-rh.noarch 0:2-4.el6.centos
#5 13.05
#5 13.05 Complete!
#5 13.19 Loaded plugins: fastestmirror, ovl
#5 13.19 Setting up Install Process
#5 13.26 Determining fastest mirrors
#5 13.77 * base: centos.host-engine.com
#5 13.77 * centos-sclo-rh: mirror.steadfastnet.com
#5 13.77 * centos-sclo-sclo: repos-tx.psychz.net
#5 13.77 * extras: repo1.dal.innoscale.net
#5 13.77 * updates: centos.host-engine.com
#5 14.97 No package devtoolset-6 available.
#5 15.08 No package devtoolset-6-libatomic-devel available.
#5 15.14 Error: Nothing to do
------
failed to solve with frontend dockerfile.v0: failed to build LLB: executor failed running [/bin/sh -c yum -y install centos-release-scl && yum -y install devtoolset-6 devtoolset-6-libatomic-devel]: runc did not terminate sucessfully
Seems odd as I don't think the dockerfile for this tool has changed between rc2 and the HEAD of develop, but I'm just getting used to this repo, so I could be mistaken.
With openlane rc4, if the design is missing the config files make regression will crash.
<prompt>:openlane <user>$ make regression
cd <local_dir> && \
docker run -it -v <local_dir>:/openLANE_flow -v <local_dir>:<local_dir> -e PDK_ROOT=<pdk_dir> -u 501:20 efabless/openlane:rc4 sh -c "python3 run_designs.py -dts -tar logs reports -html -t TEST_SW_HD -th 4 -p 0"
Traceback (most recent call last):
File "run_designs.py", line 346, in <module>
design_name= utils.get_design_name(design, config)
File "/openLANE_flow/scripts/utils/utils.py", line 55, in get_design_name
config_file_opener = open(config_file, "r")
FileNotFoundError: [Errno 2] No such file or directory: '/openLANE_flow/./designs/biriscv_tcm//config.tcl'
make: *** [regression] Error 1
Maybe change get_design_name in scripts/utils/utils.py to something like
try:
config_file_opener = open(config_file, "r")
configs = config_file_opener.read()
config_file_opener.close()
except FileNotFoundError:
print ("{design} is missing its config file!".format(design=design))
return "INVALID DESIGN PATH"
Can we take any independent RTL to perform PnR?
when I tried the following command
git clone [email protected]:google/skywater-pdk.git
I am getting this
Cloning into 'skywater-pdk'...
[email protected]: Permission denied (publickey).
fatal: Could not read from remote repository.
Please make sure you have the correct access rights
and the repository exists.
Add option to set threads:#CORES to TritonRoute.params so my computer stops yawning while routing
I have successfully executed the top-level flow.tcl in the docker on one of the example designs (chacha in this case). Are there any results that provide the final die area required for the design (and what units the measurements are in)?
Thank you for the help!
Kindly help me for the below simple 1-bit binary full adder's RTL_to_GDSII operation
module fa(a,b,c,sum,co);
input a,b,c;
output sum,co;
assign sum=a^b^c;
assign co=a&b|a&c|b&c;
endmodule
Makefile:42: ***
PDK_ROOT is not set <<<<<<<<<<<<<<<<<<<<
. Stop.
Not a good idea to keep telling people to modify their boot loader configuration. See https://github.com/efabless/openlane/issues/9 for details.
Should help with running natively as well.
Hello, we have a team of multiple users working on an Amazon Web Services (AWS) Ubuntu machine and we would like all the users to run the docker container and the complete openlane flow. For that purpose I placed the openlane directory in the /home directory of the machine so that everyone can access it. But now docker requires sudo privileges to run which is not what we need. Is there a way to set up the openlane flow so that multiple users can work with the docker container and synthesize the designs?
Using rc4.
I have synthesized the inverter to try running a spice simulation.
The generated spice file was designs/inverter/runs/07-11_21-11/results/magic/inverter.spice.
I expected a full parasitic extraction netlist, but I am actually more happy with what I got, which is a netlist of standard cells (including capacitors filler and tap cells).
After I tried to create an example simulation and I got the next error.
Error: too few nodes: xfiller_0_15 vgnd vpwr sky130_fd_sc_hd__decap_12
The affected line in the spice netlist is:
XFILLER_0_15 VGND VPWR sky130_fd_sc_hd__decap_12
The problem seems two missing connections for ports VNB & VPB for a decap cell.
.subckt sky130_fd_sc_hd__decap_12 VGND VNB VPB VPWR
M1000 VPWR VGND VPWR VPB phighvt w=870000u l=4.73e+06u
+ ad=4.524e+11p pd=4.52e+06u as=0p ps=0u
M1001 VGND VPWR VGND VNB nshort w=550000u l=4.73e+06u
+ ad=2.86e+11p pd=3.24e+06u as=0p ps=0u
.ends
The same ports are also present on filler cells and also not connected in the netlist.
.subckt sky130_fd_sc_hd__fill_1 VGND VNB VPB VPWR
.ends
Interestingly, sub-circuit instances are also not named consistently.
XFILLER_*_* is used for decap and fill cells, some instances use the XPHY_* name.
Hello I am Unable to clone the skywater-pdk using the following command;
git clone https://github.com/google/skywater-pdk
Hi,
I want to know if openlane supports on-the-fly configuration changes.
For instance: for a design, say picorv32a, I chose my FP_CORE_UTIL as 50 (in ../picorv32a/config.tcl) ..I do till run_floorplan stage (in interactive flow) but now I want to change FP_CORE_UTIL to 60. So in this case, post modifying config.tcl, do I need to run from the beginning of flow or just running run_floorplan again take FP_CORE_UTIL as 60 ?
Because the latter isn't updating my config.tcl (../openlane/designs/runs/date/config.tcl).
Let's take the following example
module fa(a,b,c,sum,co);
input a,b,c;
output sum,co;
assign sum=a^b^c;
assign co=a&b|a&c|b&c;
endmodule
In the above example there is no clock, how do I modify the config.tcl
I tried commenting the following it is give error, and by keeping that as well the same issue. Please help.
set ::env(CLOCK_PERIOD) "10"
set ::env(CLOCK_PORT) "clk"
set ::env(CLOCK_NET) $::env(CLOCK_PORT)
Hi,
I think the configurations for io pin placement during floorplanning is picked by openlane from /path/to/openlane/configuration/floorplan.tcl. However, I'm not sure of the steps to perform custom pin-placement during Floorplanning.
For instance, for design, say picorv32a, if I want my 'resetn' pin to be precisely in the left, lower-half section; what all modifications do I need to do.
Build Information : Docker Build on Ubuntu 20.04
PDK Information : sky130A, variant - sky130_fd_sc_hd, typical op condition - tt_025C_1v80
I have observed the following error on two of my designs and on spi controller (raven_spi) from Raven-SOC.
The flow exits after track assignment begins when using routing strategies 0 through 3. I have used the inputs from tritonRoute.param file and have successfully ran TritonRoute on those independently. All the designs were successfully routed on routing strategy 14.
Screenshot of PDK_PDK_VARIANT_config.tcl used on raven_spi is attached below:
I am unsure where the problem is. Kindly look into it.
Thank you.
We have a design that instantiates a submodule. When converting that module to a hard block, we leave the parameters in:
mac_cluster #(
.MAC_CONF_WIDTH(MAC_CONF_WIDTH),
.MAC_MIN_WIDTH(MAC_MIN_WIDTH),
.MAC_MULT_WIDTH(MAC_MULT_WIDTH),
.MAC_ACC_WIDTH(MAC_ACC_WIDTH),
.MAC_INT_WIDTH(MAC_INT_WIDTH)
) macaroni ( /* redacted */ );
Even though the mac_cluster module is marked as (* blackbox *), Yosys generates this instantiation in the output verilog:
mac_cluster #(
.MAC_ACC_WIDTH(32'sb00000000000000000000000000100000), /* this is the error line */
.MAC_CONF_WIDTH(32'sb00000000000000000000000000000100),
.MAC_INT_WIDTH(32'sb00000000000000000000000000101000),
.MAC_MIN_WIDTH(32'sb00000000000000000000000000001000),
.MAC_MULT_WIDTH(32'sb00000000000000000000000000010000)
) macaroni ( /* redacted */ );
The parameters appear to be a problem for verilog2def, which emits this error to its log and then fails to include the module in the output DEF:
Error: /openLANE_flow/designs/250_mac_tile/runs/debug/results/synthesis/mac_tile.synthesis.v, line 165106 syntax error, unexpected '.'.
However, the flow continues, later failing when the macro cannot be found to place.
Placing the following macros:
{'macaroni': ['5000', '5000', 'N']}
Design name: mac_tile
Traceback (most recent call last):
File "/openLANE_flow/scripts/manual_macro_place.py", line 115, in <module>
assert not macros, ("Macros not found:", macros)
AssertionError: ('Macros not found:', {'macaroni': ['5000', '5000', 'N']})
I have just updated to rc3, but I cannot build any design as I get a segmentation fault in openroad (for example on spm).
Maybe I am alone with this issue, but rc2 was working correctly.
Do you have any tips to investigate such as crash ? In particular, any easy way to get all the environment variables so that a binary can be executed under a debugger ?
make test
cd /home/zakir/openlane &&
docker run -it -v /home/zakir/openlane:/openLANE_flow -v /home/zakir/opl/:/home/zakir/opl/ -e PDK_ROOT=/home/zakir/opl/ -u 0:0 openlane:rc3 bash -c "./flow.tcl -design spm -tag openlane_test -overwrite"
[INFO]:
___ ____ ___ ____ _ ____ ____ ___
/ \ | \ / ]| \ | | / || \ / ]
| || o ) [ | _ || | | o || _ | / [
| O || / ]| | || |_ | || | || ]
| || | | [ | | || || _ || | || [_
_/ || ||||||||||||||_____|
[INFO]: Version: rc3
[INFO]: Running non-interactively
[INFO]: Using design configuration at /openLANE_flow/designs/spm/config.tcl
[INFO]: PDKs root directory: /home/zakir/opl/
[INFO]: PDK: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
couldn't read file "/home/zakir/opl//sky130A/libs.tech/openlane/config.tcl": no such file or directory
while executing
"source $pdk_config"
(procedure "prep" line 123)
invoked from within
"prep {}$args"
(procedure "run_non_interactive_mode" line 9)
invoked from within
"run_non_interactive_mode {}$argv"
invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
puts_info "Running interactively"
if { [info exists arg_values(..."
(file "./flow.tcl" line 160)
Makefile:86: recipe for target 'test' failed
make: *** [test] Error 1
Hi All,
I am working on a 16-Bit processor I wrote many years ago (named Pico16) using the OpenLane flow. I am using the Docker image (downloaded last week) and have been able to get it all the way through the flow several times. I have also been able to get a couple of the examples to run.
I am making a few extensions to my Pico16 processor ISA, and occasionally when I run "flow.tcl -design pico16", I get the following error (followed by some python error messages):
Warning: Overlap check failed (2).
PHY_470 overlaps PHY_1
PHY_4877 overlaps PHY_429
[ERROR]: during executing: "openroad -exit /openLANE_flow/scripts//openroad/or_diodes.tcl |& tee >&@stdout /openLANE_flow/designs/pico16/runs/04-09_19-06//logs//placement/diodes.log"
[ERROR]: Last 10 lines:
child process exited abnormally
[ERROR]: Please check openroad log file
[ERROR]: Dumping to /openLANE_flow/designs/pico16/runs/04-09_19-06//error.log
Is this a known issue with a possible workaround?
Thanks,
Ken
I First tried openlane rc3 last week, I was able to install all dependencies and to add myself to the docker group.
I was able to run make test without issues. This is on Ubuntu 20.04.
Today I tried rc4 twice, the second time with a thorough cleanup (not sure about docker).
make test ends with the next message:
[INFO]: /openLANE_flow/designs/spm/runs/openlane_test/results/magic/spm.spice against /openLANE_flow/designs/spm/runs/openlane_test/results/lvs/spm.lvs.powered.v
[INFO]: Running Antenna Checks...
[INFO]: Running OpenROAD Antenna Rule Checker...
[INFO]: Generating Final Summary Report...
[SUCCESS]: Flow Completed Without Fatal Errors.
/bin/sh: 1: [[: not found
Basic test failed
Hello, I was running the design with the memory module set as a black_box as mentioned in https://github.com/efabless/openlane/blob/master/doc/chip_integration.md by adding the below two variables in the config.tcl script:
set ::env(VERILOG_FILES_BLACKBOX) $::env(OPENLANE_ROOT)/designs/memory_core/src/sram.v
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
My design directory src contains the following three files:
memory_core.vcore.vsram.vWith memory_core being the top module.
However, after synthesis I realized that although there were no errors but no mapping was done and an empty netlist was generated which contained only these lines:
module memory_core(clk, reset);
input clk;
input reset;
endmodule
I went through the log files and observed that it is not creating anything. It had the following the messages:
Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module memory_core:
created 0 $alu and 0 $macc cells
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
Extracting gate netlist of module `\memory_core' to `/tmp/yosys-abc-BDpQ39/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map
(Should this be filed with OpenROAD instead?)
I configured OpenLane and ran ./flow.tcl -design $DESIGN in the docker container. I'm running the rc2 release.
TritonRoute segfaulted and the whole flow died. I'm attaching the entire run output directory.
Please let me know if there's a way I can enable or provide more useful debug information.
Design source:
aryap_riscv_core.151.tar.gz
While trying to use Openlane flow for the Aardonyx SoC designed at IIT Madras, there is a crash encountered during the run of Magic. The Ubuntu terminal hangs while writing to the LEF file after about 45 minutes of the start of Magic run. My system has 6GB of RAM and 6GB of swap space on top of it but the issue persists. I would like to know the recommended system RAM requirements for running Magic and the subsequent DRC and LVS checks. I would also like to know if there is any way to circumvent the issue faced. Do let me know if I need to provide any further details.
Config Details:
set ::env(CLOCK_PERIOD) 11
set ::env(RUN_MAGIC) 1
set ::env(RUN_ROUTING_DETAILED) 1
set ::env(RUN_SIMPLE_CTS) 0
set ::env(CLOCK_TREE_SYNTH) 1
Verilog Source Directory:
aardonyx_soc.tar.gz
Tool hangs trying to resolve symetries
Class: sky130_fd_sc_hd__fill_2 instances: 26035
Class: sky130_fd_sc_hd__decap_12 instances: 6555
Class: sky130_fd_sc_hd__nor2_4 instances: 1057
Circuit contains 12008 nets, and 5 disconnected pins.
Circuit 1 contains 106880 devices, Circuit 2 contains 106880 devices.
Circuit 1 contains 12008 nets, Circuit 2 contains 12008 nets.
Circuits match with 5586 symmetries.
Netlists match with 5586 symmetries.
Hello,
I'm trying to run some tests for the caravel (eg veriog/dv/caravel/mgmt_soc/uart). These tests seem to expect some verilog model files, such as libs.ref/sky130_fd_io/verilog/sky130_fd_io.v, to exist inside ${PDK_ROOT}/sky130A. These files do not exist anywhere in my ${PDK_ROOT}, and I've tried rebuilding just in case.
Has something changed here that needs to be updated in caravel? Is something going wrong with my PDK build? Any help would be much appreciated!
Thanks and Best Regards,
Matthew
Adding this to the spm config.tcl file (plus others I've tried) causes errors such as the one in this gist:
set ::env(DIODE_INSERTION_STRATEGY) 2
The default value (3?) doesn't seem to have this issue.
The logs in the linked gist are from running in docker on develop (commit d03377b)
./flow -interactive -design spm -tag run1 -overwrite
% require package openlane 0.9
% prep -design spm -tag run1 -overwrite
Fresh setup of PDKs and OpenLane rc3. Using sky130_fd_sc_hdll library.
Ran the simple ./flow.tcl -design spm and got the following:
[OpenPhySyn] [2020-10-20 07:05:51.834] [info] Invoking repair_timing transform
[OpenPhySyn] [2020-10-20 07:05:51.840] [info] Buffer library: sky130_fd_sc_hdll__buf_4, sky130_fd_sc_hdll__buf_8, sky130_fd_sc_hdll__buf_1
[OpenPhySyn] [2020-10-20 07:05:51.840] [info] Inverter library: None
[OpenPhySyn] [2020-10-20 07:05:51.840] [info] Buffering: enabled
[OpenPhySyn] [2020-10-20 07:05:51.840] [info] Driver sizing: enabled
[OpenPhySyn] [2020-10-20 07:05:51.840] [info] Pin-swapping: enabled
[OpenPhySyn] [2020-10-20 07:05:51.840] [info] Mode: Timing-Driven
[OpenPhySyn] [2020-10-20 07:05:51.840] [info] Iteration 1
[ERROR]: during executing: "Psn /openLANE_flow/scripts/openPhySyn.tcl |& tee >&@stdout /openLANE_flow/designs/spm/runs/20-10_07-05/logs/placement/openphysyn.log"
[ERROR]: Last 10 lines:
child killed: segmentation violation
[ERROR]: Please check Psn log file
[ERROR]: Dumping to /openLANE_flow/designs/spm/runs/20-10_07-05/error.log
while executing
"try_catch Psn $::env(SCRIPTS_DIR)/openPhySyn.tcl |& tee $::env(TERMINAL_OUTPUT) $::env(openphysyn_log_file_tag).log"
(procedure "run_openPhySyn" line 7)
invoked from within
"run_openPhySyn"
(procedure "run_placement" line 13)
invoked from within
"run_placement"
(procedure "run_non_interactive_mode" line 13)
invoked from within
"run_non_interactive_mode {*}$argv"
invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
puts_info "Running interactively"
if { [info exists arg_values(..."
(file "./flow.tcl" line 160)
dmesg reports the segfault as:
[15672.622994] Psn[38572]: segfault at 18 ip 00000000008962cf sp 00007fff5f687630 error 4 cpu 4 in Psn[400000+15d6000]
[15672.623000] Code: 89 ef ff 50 10 4c 89 ef 84 c0 49 8b 45 00 0f 84 e7 00 00 00 ff 50 18 48 8b 7b 20 49 89 c7 48 8b 07 4c 89 fe ff 90 58 02 00 00 <48> 8b 78 18 49 89 c6 e8 f5 2d fb ff 48 8b 7b 48 4c 89 fe 84 c0 75
If it helps, host distro is Clear Linux.
I tried to install openlane (branch rc1) following the instructions (cd openlane/docker_build ; make merge). But the build always fails with:
Step 2/22 : RUN yum install -y git tcl tk libjpeg libgomp libXext libSM libXft libffi cairo gettext Xvfb
---> Running in 4f9707bae11a
The command '/bin/sh -c yum install -y git tcl tk libjpeg libgomp libXext libSM libXft libffi cairo gettext Xvfb' returned a non-zero code: 139
Any clue as to what is going on here?
I have tried using the OpenLane flow for the aardonyx SoC developed at IIT Madras, India. An error is encountered during the synthesis step using Yosys and ABC.
.
The error message reads as below:
67.1. Executing OPT_EXPR pass (perform const folding).
terminate called after throwing an instance of 'std::out_of_range'
what(): Cell::getParam()
[ERROR]: during executing: "yosys -c /openLANE_flow/scripts//synth.tcl -l /openLANE_flow/designs/aardonyx/runs/28-07_19-08//logs/synthesis/yosys.log |& tee >&@stdout"
[ERROR]: Last 10 lines:
child killed: SIGABRT
I'm on rc3 -
The yosys_rewrite_verilog.tcl step of this flow is taking a strangely long time. yosys is consuming ~92 GB of RAM and has been spinning a core at ~100% for 16.5 hours.
The command is yosys -c /openLANE_flow/scripts/yosys_rewrite_verilog.tcl -l /openLANE_flow/designs/151/runs/06-10_16-40/logs/synthesis/yosys_rewrite_verilog.log, but the log file is empty. I believe it's still in the read_verilog step of the script but I can't really be sure. The design is the same as in #39.
I had a stab at debugging yosys; it gets stuck in a recursive call and I couldn't observe progress over a few hours. It might just be really slow.
I built Yosys at HEAD instead and this problem seems to have gone away, with the rewrite step now completing in ~7 hours.
Has anyone else run into this problem with the yosys commit in rc3? (347dd01c2f7dff6e8222c5f9d360f84a17c937b5)
When attempting to run the spm design with the _hs cells there is a segmentation fault failure during antenna checks. I have run the same design with the recommended _hd cells with no problem. Therefore, I assume it's something in the setup of the _hs cells.
Output of terminal:
Running antenna checks.
[ERROR]: during executing: "magic -noconsole -dnull -rcfile /openLANE_flow/designs/spm/runs/06-08_21-36//tmp//magic_antenna.magicrc /openLANE_flow/designs/spm/runs/06-08_21-36//tmp//magic_antenna.tcl </dev/null |& tee >&@stdout /openLANE_flow/designs/spm/runs/06-08_21-36//logs/magic/magic_antenna.log"
[ERROR]: Last 10 lines:
child killed: segmentation violation
[ERROR]: Please check magic log file
[ERROR]: Dumping to /openLANE_flow/designs/spm/runs/06-08_21-36//error.log
error.log:
during executing: "magic -noconsole -dnull -rcfile /openLANE_flow/designs/spm/runs/06-08_21-36//tmp//magic_antenna.magicrc /openLANE_flow/designs/spm/runs/06-08_21-36//tmp//magic_antenna.tcl </dev/null |& tee >&@stdout /openLANE_flow/designs/spm/runs/06-08_21-36//logs/magic/magic_antenna.log"
Last 10 lines:
child killed: segmentation violation
PROC: Start NESTEROV's Optimization
PROC: Global Lagrangian Multiplier is Applied
ITER: 0
HPWL=382.550232
OVFL=0.725638
HPWL=(159.536499, 223.013733)
POTN=2.085887E+08
PHIC=1.524986E-09
GRAD=4.210845E-01
NuBT=0
CPU =0.000000
ITER: 1
HPWL=376.941772
OVFL=0.697518
HPWL=(154.447601, 222.494186)
POTN=1.924570E+08
PHIC=1.601235E-09
I have a design that synthesizes properly on rc4 but fails when I updated OpenLane to develop (nothing else changed). The advice from Slack is to increase the clock period and double check the clock, but those did not resolve the issue. Below are more details:
Error:
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load $cap_load [all_outputs]
tns -3.94
wns -2.24
[ERROR]: during executing: "sta /openLANE_flow/scripts/sta.tcl |& tee >&@stdout /openLANE_flow/designs/mac_cluster/runs/17-11_00-16/logs/synthesis/opensta.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child killed: segmentation violation
[ERROR]: Please check sta log file
[ERROR]: Dumping to /openLANE_flow/designs/mac_cluster/runs/17-11_00-16/error.log
opensta.log (it's short so posting directly here)
OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>
This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details.
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Warning: /home/anson/cs250_pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /home/anson/cs250_pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 40.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 40.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load $cap_load [all_outputs]
tns -3.94
wns -2.24
Config:
# User config
set ::env(DESIGN_NAME) mac_cluster
# Change if needed
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
# Fill this
set ::env(CLOCK_PERIOD) "200"
set ::env(CLOCK_PORT) "clk"
set ::env(SYNTH_MAX_FANOUT) 7
set ::env(PL_TARGET_DENSITY) 0.35
set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
source $filename
}
Note: I've also tried changing the parameters a bit to see if anything changes, but the error is consistent.
Openlane commit: (I tried 2, both fail: d03377b84212527a269dfc58bb637a9e921af150 (Nov 13), d9584fd1923a525de4a69b3da5a9d6f59fa25d9f (newest as of Nov 16))
Repo of OpenLane design: https://github.com/TsaiAnson/exampleDesignOpenLaneMACCluster
^ This design synthesizes fine on rc4 while fails on develop.
Slack Post (openlane channel): https://skywater-pdk.slack.com/archives/C016H8WJMBR/p1605399551389700
Could someone take a look for the issue? Thanks in advance.
This can be seen by running the spm design with the FP_CORE_UTIL set to 15. This will cause the following error:
Warning: Overlap check failed (2).
PHY_196 overlaps PHY_1
PHY_961 overlaps PHY_179
[ERROR]: during executing: "openroad -exit /openLANE_flow/scripts//openroad/or_diodes.tcl |& tee >&@stdout /openLANE_flow/designs/spm/runs/25-07_02-57//logs//placement/diodes.log"
[ERROR]: Last 10 lines:
child process exited abnormally
[ERROR]: Please check openroad log file
[ERROR]: Dumping to /openLANE_flow/designs/spm/runs/25-07_02-57//error.log
The README.md for openlane defines following .libs as defaults for min and max analysis..
| LIB_MIN | Library used for min delay calculation during STA.
(Default:./pdks/ef-skywater-s8/EFS8A/libs.ref/liberty/efs8hd/efs8hd_ss_1.60v_100C.lib) |
| LIB_MAX | Library used for max delay calculation during STA.
(Default:./pdks/ef-skywater-s8/EFS8A/libs.ref/liberty/efs8hd/efs8hd_ff_1.95v_-40C.lib) |
Shouldn't it be the other way round, i.e.,
'ss' .lib as LIB_MAX and 'ff' .lib as LIB_MIN ?
It is probably a good idea to clone the library submodules in "shallow" mode.
git submodule update --init libraries/sky130_fd_sc_hd/latest
See related issue @ google/skywater-pdk#108
The opensta.min_max.rpt file seems to show min and max slack data. What units are being used in this report? For example, my opensta.min_max.rpt has:
...
2.00 12.00 clock vclk (rise edge)
0.00 12.00 clock network delay (ideal)
0.00 12.00 clock reconvergence pessimism
12.00 ^ _35045_/CLK (sky130_fd_sc_hd__dfxtp_4)
-0.09 11.91 library setup time
11.91 data required time
11.91 data required time
-11.08 data arrival time
0.83 slack (MET)
I would have guessed that these are in ns, but my .tcl and .sdc files specify 10ns clock periods:
config.tcl
set ::env(CLOCK_PERIOD) "10.0"
sky130A_sky130_fd_sc_hd_config.tcl
set ::env(CLOCK_PERIOD) "10.000"
project.sdc
set_units -time ns create_clock [get_ports clk] -name core_clock -period 10
Hi, I have cloned the repository in the aws Ubuntu instance in the following path /home/merlproj/backend-tools. I have built the skywater-pdk and installed it using the open_pdk. When I run the docker container from the path /home/merlproj/backend-tools/openlane the bash-4.1 shell comes up. I then run the script ./flow.tcl and it shows the following error:
I then tried to give the permission to flow.tcl file but the bash-4.1 does not recognise sudo command.
Hi,
I am getting error on running run_placement. Replace is causing the issue.
[INFO] 80pCellArea = -nan [INFO] FillerInit: TotalFillerArea = 821.911865 [INFO] FillerInit: NumFillerCells = -2147483648 [INFO] FillerInit: FillerCellArea = -nan [INFO] FillerInit: FillerCellSize = (-nan, -nan) [ERROR]: during executing: "replace < /openLANE_flow/scripts//replace_gp.tcl |& tee >&@stdout /openLANE_flow/designs/AMUX2_3V_top/runs/19-08_07-19//logs/placement/replace.log" [ERROR]: Last 10 lines: child killed: segmentation violation
After debugging, I understood that rep place_cell_nesterov_place is causing error which is present in replace_gp.tcl
Can someone please help?
Hello,
I have an segmentation fault violation during the detailed placement phase while using DFFRAM from caravel under USE_CUSTOM_DFFRAM macro with 256 mem words. The log says that the def output file was successfully written but I have observed that the file is not fully written. The flow then moves on to placement check and ends with a segmentation fault and exit error code 1. The error log and opendp log are attached here.
The resultant placement def file is attached here for your reference.
I am using RC4 with relevant open_pdk and skywater tags based on the flow. It is the same for both local docker image and efabless/openlane:rc4 docker image. The config, pdn and pin order files are same as those present in caravel.
I am sure the DFFRAM verilog file in caravel wasn't implemented as is in the macro posted. Verilog wise, the pass mux might be the root of all problems, the way it is implemented. But I am posting this issue here because the placement def file output is more puzzling to me. The Replace def file in temp directory is written fully. Why is the def file not being completely written and how is the flow deciding that it has been successfully written and proceeding to placement checks? Kindly let me know if you are able to replicate this issue. I am unable to figure out why this behavior is being exhibited.
Thank you.
The current work around is:
set ::env(CLOCK_PERIOD) 0
set ::env(CLOCK_TREE_SYNTH) 0
While trying to use Openlane flow for the Aardonyx SoC designed at IIT Madras, there is a crash encountered during the routing process using FastRoute.
The error message reads as below:
terminate called after throwing an instance of 'std::bad_alloc'
what(): std::bad_alloc
[ERROR]: during executing: "openroad -exit /openLANE_flow/scripts//openroad/or_route.tcl |& tee >&@stdout /openLANE_flow/designs/aardonyx/runs/10-08_13-50//logs/routing/fastroute.log"
[ERROR]: Last 10 lines:
child killed: SIGABRT
FastRoute Log:
fastroute.log
Configuration details:
set ::env(CLOCK_PERIOD) 11
set ::env(ROUTING_STRATEGY) 0
set ::env(GLB_RT_ADJUSTMENT) 0
set ::env(GLB_RT_L1_ADJUSTMENT) 0.99
set ::env(GLB_RT_L2_ADJUSTMENT) 0
set ::env(GLB_RT_MINLAYER) 1
set ::env(GLB_RT_MAXLAYER) 6
set ::env(GLB_RT_UNIDIRECTIONAL) 1
set ::env(GLB_RT_ALLOW_CONGESTION) 0
set ::env(GLB_RT_OVERFLOW_ITERS) 50
SoC Verilog Source Directory:
aardonyx_soc.tar.gz
Kindly look into the issue. Do let me know if I need to provide any further details.
Running the OpenLane flow on the trivial latch
module test_latch (
input wr_en,
input a,
output b
);
reg a_latch;
always @(*) begin
if (wr_en)
a_latch = a;
end
assign b = a_latch;
endmodule
fails synthesis. Yosys correctly infers a $_DLATCH_P_ primitive but cannot map this to a suitable cell, like Skywater 130's dlxtp cell. Cadence Genus will do this:
module test_latch(a, wr_en, b);
input a, wr_en;
output b;
wire a, wr_en;
wire b;
wire n_0, n_2;
sky130_fd_sc_hd__inv_8 g4(.A (n_0), .Y (b));
sky130_fd_sc_hd__inv_1 g5(.A (n_2), .Y (n_0));
sky130_fd_sc_hd__dlxtp_1 a_latch_reg(.GATE (wr_en), .D (a), .Q (n_2));
endmodule
Yosys seems to need special tech-mapping for this primitive, which is provided by (for example) FPGA targets, but not for Skywater.
I created a test mapping /openLANE_flow/dlatchp.v
module \$_DLATCH_P_ (input E, input D, output Q);
sky130_fd_sc_hd__dlxtp_1 _TECHMAP_REPLACE_ (
.GATE(e),
.D(D),
.Q(Q));
endmodule
and inserted techmap -map /openLANE_flow/dlatchp.v into scripts/synth.tcl to make sure the mapping was run. This seems to correct the issue and synthesis passes. The flows then continues before segfaulting on the replace command. So maybe I did it wrong.
Dear Sir,
I tried installing the OPENLANE in my Mac OS.
I tried installing the SkyWater PDK . I am facing the following issue given in the attachment.
Kindly help me for successful installation .
with regards
Srinath
I had followed every single step given, but I am facing the following Issue.
[INFO]: Version: rc1
[INFO]: Using design configuration at /openLANE_flow/designs/spm/config.tcl
couldn't read file "/openLANE_flow/pdks//sky130A/libs.tech/openlane/config.tcl": no such file or directory
while executing
"source $pdk_config"
(procedure "prep" line 86)
invoked from within
"prep {}$args"
(procedure "run_non_interactive_mode" line 7)
invoked from within
"run_non_interactive_mode {}$argv_copy"
invoked from within
"if { [info exists flags_map(-interactive)] ||
[info exists flags_map(-it)] } {
if { [info exists arg_values(-file)] } {
run_file [file normali..."
(file "./flow.tcl" line 136)
From openroad synth.tcl
set vIdirsArgs ""
if {[info exist ::env(VERILOG_INCLUDE_DIRS)]} {
foreach dir $::env(VERILOG_INCLUDE_DIRS) {
lappend vIdirsArgs "-I$dir"
}
set vIdirsArgs [join $vIdirsArgs]
}
# read verilog files
foreach file $::env(VERILOG_FILES) {
read_verilog -defer -sv {*}$vIdirsArgs $file
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