Comments (7)
@growly: As per our discussion yesterday, I have run your design (on develop - rc3-to-be) with a resized synthesized memory (~25% of the current one) currently with 40% core utilization, 0.3 target placement density, 30ns clock period, and it got all the way to a GDSII with ~2 violations (that's where exploration comes in as discussed). (EDIT: I re-ran it again with 30% core utilization and 0.2 placement density, and I got DRC- and LVS- clean layouts -- This is probably a good data point even if you have a bigger synthesized memory).
I am doing another run with 50% synthesized memory on the side, but I expect that it will still take a while.
Have you had a chance to re-run your design with TR14 and/or resizing the synthesized memory? From my observations, running your design as it is would require at least 16 GB of memory just during synthesis, and depending on the CPU and the design configuration, it is expected to take around 16-18 hours.
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I have been running the new rc3 flow for about the past week. It definitely seems more stable. I certainly haven't run into any segfaults this time.
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@growly: That's great to hear!
Would you mind sharing your design in the repo (this way, we'll always be sure that it's able to pass the flow)?
You can do that by submitting a PR to the develop branch in which you put your design and configuration under ./designs/
. Make sure to include a LICENSE accrediting yourself as the developer of this Verilog code. Of, course we'll understand if you don't want to share it on the repo, so no pressure.
Also, I'll close this issue since it no longer stands.
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@growly, can you share with me the configuration files you fed to flow.tcl? I'm aware you included the config.tcl that gets generated inside the run directory. But, just to save time and allow me to replicate what happened to you, could you share the one you used?
Also, as a start, I'd advise using TR14 by setting ROUTING_STRATEGY to 14.
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@agorararmard No problem, I think it's this one:
(This is just gzip
ped, not tar
'd)
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@growly could you try rc3 and tell us if you have any trouble?
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Thanks for the updates, I'm working on reproducing your results!
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