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Arya Reais-Parsi's Projects

bfg icon bfg

An Open-Source Silicon Compiler for Reduced-Complexity Reconfigurable Fabrics

blifdot icon blifdot

Generate graphviz DOT format from BLIF

caravel icon caravel

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

cbag icon cbag

A C++ VLSI circuit schematic and layout database library

cs50 icon cs50

Introduction to Computer Science exercises - CS50

dffram_lut icon dffram_lut

Standard Cell Library based Memory Compiler using DFF cells

hammer icon hammer

HAMMER: Highly Agile Masks Made Effortlessly from RTL

hdl21 icon hdl21

Hardware Description Library

openlane icon openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

openroad-flow-scripts icon openroad-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

tesla-osc icon tesla-osc

FPGA implementation of OSC control for tesla coils

vlsir icon vlsir

Interchange formats for chip design.

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