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aklny

This is a food ordering service website.

alu32-optimized

This is an optimized version for an ALU coded in Verilog

caravel

Caravel is a standard prototyping platform to be used by IP/IC developers

caravel-1

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

dictionary-cpp

This is a c++ implementation for python dictionary maintaining insertion order while having fast remove insert search access of an std::map

dwarf-rv32ic-andassemblytestgenerator

This is a simulator + verilog RTL of a RV32i CPU with C extension support. The Repo also include a random test generator that was used to stress-test the CPU

i2c-verilog

This is an I2C implementation using Verilog

magic

Magic VLSI Layout Tool

morphlelogic

Morphle Logic V1.0, an open hardware asynchronous runtime reconfigurable array ARRA or PPL,FPGA,CPLD

netgen

Netgen complete LVS tool for comparing SPICE or verilog netlists

network-congestion-resolver-matlab

This is a car network congestion resolver coded in matlab

open_pdks

PDK installer for open-source EDA tools and toolchains. Distributed with a setup for the Google/SkyWater 130nm process.

openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

openroad

OpenROAD's unified application implementing an RTL-to-GDS Flow

own-implementation-neural-network

This is an own implementation of a dynamic Neural Network coded in python

p2p-filesharing-tcp

This a Peer to Peer file sharing application build on top of TCP Communication

portable-heart-monitor-with-stm32

This is an implementation of a portable heart monitor using the STM32 CubeMX and a processing mobile application

quine-mccluskey-implementation

This is a dynamic Quine Mccluskey implementation in C++

rca-cla-csa-signed-unsigned-nxm-multiplier

This is an implementation of some adders: Ripple Carry Adder, Carry Select Adder, and Carry Lookahead Adder. And nxm dynamic parallel multipliers: Signed, and Unsigned using Verilog

repob

rv32i-disassembler-simulator-and-memory-hierarchy-simulator

RV32i Disassembler, Simulator, and Memory Hierarchy Simulator in c++

sar-adc-controller

This is a SAR ADC Controller verilog implementation

self-navigating-car-with-track-based-system

Designed and tested Car that self-navigates itself and stores its track which using the UART is inputted and drawn into a GUI. Or the user can draw the track into the GUI, it will be stored in the car which will move according to the track.

serial-parallel-multiplier-verilog

This is a Serial Parallel Multiplier coded in Verilog

simple-integer-machine

Simple Integer Machine Processor simulator using C++ and an object oriented design

simple-integer-machine-part2

Simple Integer Machine Multiple-Processors simulator using C++ and an object oriented design

skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

skywater-pdk-actions

GitHub Actions for usage with Google's 130nm manufacturable PDK for SkyWater Technology found @ https://github.com/google/skywater-pdk

skywater-pdk-libs-sky130_fd_sc_hd

sorted-array

This is a sorted array showing basic understanding of c++ object oriented programming