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A logic synthesis tool

amf-placer

AMF-Placer: An open-source analytical mixed-size FPGA placer

argparse

Argument Parser for Modern C++

arl

lists of most popular repositories for most favoured programming languages (according to StackOverflow)

awesome-eda

circuit_training

clash

A rule-based tunnel in Go.

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

d2l-zh

《动手学深度学习》：面向中文读者、能运行、可讨论。英文版即伯克利“深度学习导论”教材。

dreamplace

Deep learning toolkit-enabled VLSI placement

dynamatic

eda-wiki

EDA wiki

edalize

An abstraction library for interfacing EDA tools

electron-ssr-backup

electron-ssr原作者删除了这个伟大的项目，故备份了下来，不继续开发,且用且珍惜

gprof2dot

Converts profiling output to a dot graph.

icap_controller

Include:

iverilog

Icarus Verilog

macroplacement

Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source

minisat

A minimalistic and high-performance SAT solver

new-pac

翻墙-科学上网、免费翻墙、免费科学上网、免费自由上网、fanqiang、翻墙梯子、免费软件/方法，一键翻墙浏览器，免费shadowsocks/ss/ssr/v2ray/goflyway账号/节点分享，vps一键搭建翻墙服务器脚本/教程，电脑、手机、iOS、安卓、windows、Mac、Linux、路由器翻墙

nextpnr

nextpnr portable FPGA place and route tool

nextpnr-xilinx

Experimental flows using nextpnr for Xilinx devices

openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

openroad

OpenROAD's unified application implementing an RTL-to-GDS Flow

opensta

OpenSTA engine

opentimer

A High-performance Timing Analysis Tool for VLSI Systems

parser-verilog

A Standalone Structural Verilog Parser

pugixml

Light-weight, simple and fast XML parser for C++ with XPath support

python

My Python Examples

python-1

All Algorithms implemented in Python