This library is published and maintained by Chair for VLSI Design, Diagnostics and Architecture - Faculty of Computer Science, Technische Universität Dresden, Germany http://vlsi-eda.inf.tu-dresden.de
- Overview
- Quick Start Guide
2.1. Requirements and Dependencies
2.2. Download
2.3. Configuring PoC on a Local System
2.4. Integration
2.5. Updating - Common Notes
- Cite the PoC-Library
PoC - “Pile of Cores” provides implementations for often required hardware functions such as Arithmetic Units, Caches, Clock-Domain-Crossing Circuits, FIFOs, RAM wrappers, and I/O Controllers. The hardware modules are typically provided as VHDL or Verilog source code, so it can be easily re-used in a variety of hardware designs.
All hardware modules use a common set of VHDL packages to share new VHDL types, sub-programs and constants. Additionally, a set of simulation helper packages eases the writing of testbenches. Because PoC hosts a huge amount of IP cores, all cores are grouped into sub-namespaces to build a clear hierachy.
Various simulation and synthesis tool chains are supported to interoperate with PoC. To generalize all supported free and commercial vendor tool chains, PoC is shipped with a Python based infrastructure to offer a command line based frontend.
This Quick Start Guide gives a fast and simple introduction into PoC. All topics can be found in the Using PoC section at ReadTheDocs.io with much more details and examples.
The PoC-Library comes with some scripts to ease most of the common tasks, like running testbenches or generating IP cores. PoC uses Python 3 as a platform independent scripting environment. All Python scripts are wrapped in Bash or PowerShell scripts, to hide some platform specifics of Darwin, Linux or Windows. See Requirements for further details.
- A supported synthesis tool chain, if you want to synthezise IP cores.
- A supported simulator tool chain, if you want to simulate IP cores.
- The Python 3 programming language and runtime, if you want to use PoC's infrastructure.
- A shell to execute shell scripts:
- Bash on Linux and OS X
- PowerShell on Windows
- Git command line tools or
- Git User Interface, if you want to check out the latest 'master' or 'release' branch.
- Cocotb
A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python. - OS-VVM
Open Source VHDL Verification Methodology. - UVVM
Universal VHDL Verification Methodology. - VUnit
An unit testing framework for VHDL.
All dependencies are available as GitHub repositories and are linked to PoC as Git submodules into the
PoCRoot\lib directory. See Third Party Libraries for more details on these libraries.
The PoC-Library can be downloaded as a zip-file (latest 'release' branch), cloned with git clone
or embedded with git submodule add from GitHub. GitHub offers HTTPS and SSH as transfer protocols. See
the Download page for further details. The installation directory is referred to as PoCRoot.
| Protocol | Git Clone Command |
|---|---|
| HTTPS | git clone --recursive https://github.com/VLSI-EDA/PoC.git PoC |
| SSH | git clone --recursive ssh://[email protected]:VLSI-EDA/PoC.git PoC |
To explore PoC's full potential, it's required to configure some paths and synthesis or simulation tool chains. The following commands start a guided configuration process. Please follow the instructions on screen. It's possible to relaunch the process at any time, for example to register new tools or to update tool versions. See Configuration for more details. Run the following command line instructions to configure PoC on your local system:
cd PoCRoot
.\poc.ps1 configureUse the keyboard buttons: Y to accept, N to decline, P to skip/pass a step and Return to accept
a default value displayed in brackets.
The PoC-Library is meant to be integrated into other HDL projects. Therefore it's recommended to create a library folder and add the PoC-Library as a Git submodule. After the repository linking is done, some short configuration steps are required to setup paths, tool chains and the target platform. The following command line instructions show a short example on how to integrate PoC.
The following command line instructions will create the folder lib\PoC\ and clone the PoC-Library as a
Git submodule into that folder. ProjectRoot is the directory of the hosting Git. A detailed list
of steps can be found at Integration.
cd ProjectRoot
mkdir lib | cd
git submodule add https://github.com:VLSI-EDA/PoC.git PoC
cd PoC
git remote rename origin github
cd ..\..
git add .gitmodules lib\PoC
git commit -m "Added new git submodule PoC in 'lib\PoC' (PoC-Library)."The PoC-Library should be configured to explore its full potential. See Configuration for more details. The following command lines will start the configuration process:
cd ProjectRoot
.\lib\PoC\poc.ps1 configureThe PoC-Library needs two VHDL files for its configuration. These files are used to determine the most suitable implementation depending on the provided target information. Copy the following two template files into your project's source folder. Rename these files to *.vhdl and configure the VHDL constants in the files:
cd ProjectRoot
cp lib\PoC\src\common\my_config.vhdl.template src\common\my_config.vhdl
cp lib\PoC\src\common\my_project.vhdl.template src\common\my_project.vhdlmy_config.vhdl defines two global constants, which need to be adjusted:
constant MY_BOARD : string := "CHANGE THIS"; -- e.g. Custom, ML505, KC705, Atlys
constant MY_DEVICE : string := "CHANGE THIS"; -- e.g. None, XC5VLX50T-1FF1136, EP2SGX90FF1508C3my_project.vhdl also defines two global constants, which need to be adjusted:
constant MY_PROJECT_DIR : string := "CHANGE THIS"; -- e.g. d:/vhdl/myproject/, /home/me/projects/myproject/"
constant MY_OPERATING_SYSTEM : string := "CHANGE THIS"; -- e.g. WINDOWS, LINUXFurther informations are provided at Creating my_config/my_project.vhdl.
PoC is shipped with a set of common packages, which are used by most of its modules. These packages are
stored in the PoCRoot\src\common directory. PoC also provides a VHDL context in common.vhdl , which
can be used to reference all packages at once.
Simulation projects additionally require PoC's simulation helper packages, which are located in the
PoCRoot\src\sim directory. Because some VHDL version are incompatible among each other, PoC uses
version suffixes like *.v93.vhdl or *.v08.vhdl in the file name to denote the supported VHDL version
of a file.
Some IP Cores are shipped as pre-configured vendor IP Cores. If such IP cores shall be used in a HDL project, it's recommended to use PoC to create, compile and if needed patch these IP cores. See Synthesis for more details.
The PoC-Library can be updated by using git fetch and git merge.
cd PoCRoot
# update the local repository
git fetch --prune
# review the commit tree and messages, using the 'treea' alias
git treea
# if all changes are OK, do a fast-forward merge
git mergeSee also:
- Running one or more testbenches
The installation can be checked by running one or more of PoC's testbenches. - Running one or more netlist generation flows
The installation can also be checked by running one or more of PoC's synthesis flows.
The PoC-Library is structured into several sub-folders naming the purpose of the folder like
src for sources files or tb for testbench files. The structure within these folders
is always the same and based on PoC's sub-namespace tree.
Main directory overview:
lib- Embedded or linked external libraries.netlist- Configuration files and output directory for pre-configured netlist synthesis results from vendor IP cores or from complex PoC controllers.py- Supporting Python scripts.sim- Pre-configured waveform views for selected testbenches.src- PoC's source files grouped into sub-folders according to the sub-namespace tree.tb- Testbench files.tcl- Tcl files.temp- Automatically created temporary directors for various tools used by PoC's Python scripts.tools- Settings/highlighting files and helpers for supported tools.ucf- Pre-configured constraint files (*.ucf, *.xdc, *.sdc) for supported FPGA boards.xst- Configuration files to synthesize PoC modules with Xilinx XST into a netlist.
All VHDL source files should be compiled into the VHDL library PoC. If not indicated otherwise, all
source files can be compiled using the VHDL-93 or VHDL-2008 language version. Incompatible files are
named *.v93.vhdl and *.v08.vhdl to denote the highest supported language version.
If you are using the PoC-Library, please let us know. We are grateful for your project's reference. The PoC-Library hosted at GitHub.com. Please use the following biblatex entry to cite us:
# BibLaTex example entry
@online{poc,
title={{PoC - Pile of Cores}},
author={{Chair of VLSI Design, Diagnostics and Architecture}},
organization={{Technische Universität Dresden}},
year={2016},
url={https://github.com/VLSI-EDA/PoC},
urldate={2016-10-28},
}
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