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asm_prog_ex

Exercises for Assembly language course

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

cocotbext-ahb

Cocotb AHB Extension - AHB VIP

cocotbext-axi

AXI interface modules for Cocotb

cocotbext-eth

Ethernet interface modules for Cocotb

cocotbext-i2c

I2C models for cocotb

cocotbext-pcie

PCI express simulation framework for Cocotb

cocotbext-spi

SPI modle

cocotbext-uart

UART models for cocotb

cpp_boilerplate_project

Minimized version of cpp_starter_project

cpp_starter_project

A template CMake project to get you started with C++ and tooling

dockerfiles

Some Dockerfiles for various tools

fpga-hdl_optimal_practices

Inspired by Jason Turners "C++ - Best Practices" this is an attemtp to create a "forever" changing

ghdl

VHDL 2008/93/87 simulator

ghdl-yosys-plugin

VHDL synthesis (based on ghdl)

hdlregression

jthdlc

Josh Tyler's HDL Common lib

lunarvim

🌙 LunarVim is an IDE layer for Neovim. Completely free and community driven.

nerd-fonts

Iconic font aggregator, collection, & patcher. 3,600+ icons, 50+ patched fonts: Hack, Source Code Pro, more. Glyph collections: Font Awesome, Material Design Icons, Octicons, & more

nvc

VHDL compiler and simulator

nvchad

Blazing fast Neovim config providing solid defaults and a beautiful UI, enhancing your neovim experience.

oss-cad-suite-build

Multi-platform nightly builds of open source digital design and verification tools

osvvm

OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

poc

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

pyuvm

The UVM written in Python

rust_hdl

sby

SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

setup-cpp

Install all the tools required for building and testing C++/C projects.

uvvm

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/

vcp-dsp

VHDL Library for implementing common DSP functionality.