- š Hi, Iām @nitindinnu
- š Iām interested in new stuff based on VLSI
- š± Iām pro-efficient with VLSI FRONTEND RTL design and Verification (verilog,Sytem verilog,UVM)
- šļø Iām looking to collaborate on Any project related to VLSI domain
- š« How to reach me [email protected]
nitindinnu Goto Github PK
Name: Nitin Gudeboina
Type: User
Bio: VLSI Enthusiast
Twitter: nitindinnu
Location: Hyderabad,India