yokeung Goto Github PK

captainblackboard

船长关于机器学习、计算机视觉和工程技术的总结和分享

chisel_template

flute

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

fpga-zynq

Support for Rocket Chip on Zynq FPGAs

gemmini

Berkeley's Spatial Array Generator

hdrnet

An implementation of 'Deep Bilateral Learning for Real-Time Image Enhancement', SIGGRAPH 2017

howtocook

程序员在家做饭方法指南。Programmer's guide about how to cook at home (Chinese).

isp

camera pipeline

isp_algorithm

传统的图像处理相关算法的代码实现

isp_multicam

jetson-rdma-picoevb

Minimal HW-based demo of GPUDirect RDMA on NVIDIA Jetson AGX Xavier running L4T

microzed-chronicles

Source code from the MicroZed Chronicles blog hosted by Xcell Daily Blog

oh

Silicon proven Verilog library for IC and FPGA designers

openc910

OpenXuantie - OpenC910 Core

openisp

Image Signal Processor

opensift

Open-Source SIFT Library

poc

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

pp4fpgas-cn

中文版 Parallel Programming for FPGAs

red-pitaya-notes

Notes on the Red Pitaya Open Source Instrument

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

simple-5stage-pipeline-mips-imple

和我一步一步实现一个最简单的、带数据前推及流水线暂停的32位静态五级流水MIPS

vexriscv

A FPGA friendly 32 bit RISC-V CPU implementation

vitis_libraries

Vitis Libraries

vitisai_study

xilinxtclstore

Xilinx Tcl Store

zynqnet

Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"