prajwaltr Goto Github PK
Name: Prajwal T R
Type: User
Bio: Pre final year B.E student, Interested in VLSI and Programming.
Location: Karnataka, India.
Name: Prajwal T R
Type: User
Bio: Pre final year B.E student, Interested in VLSI and Programming.
Location: Karnataka, India.
This repository will maintain simulation files and other relevant files on the Bandgap Reference IP worked on in the EICT IITG - VSD Summer Online Internship 2020
This repository contains a detailed description of a 10-bit potentiometric digital-to-analog converter. This work is carried out as a part of VSD Research Internship. The repository consists of all files required to design the PDAC. The pre-layout and post-layout simulations have also been provided with DNL and INL calculations.
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assignments
Multimedia SoC Design with Specialization on Application Acceleration with High-Level-Synthesis [2020 Fall]
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This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
Machine Learning Course
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