dpretet / async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Asynchronous dual clock FIFO

Overview

This repository stores a verilog description of dual clock FIFO. A FIFO is a convenient circuit to exchange data between two clock domains. It manages the RAM addressing internally, the clock domain crossing and informs the user of the FIFO fillness with "full" and "empty" flags.

It is widely inspired by the excellent article from Clifford Cummings, Simulation and Synthesis Techniques for Asynchronous FIFO Design.

The simulation testcases available use Icarus Verilog and SVUT tool to run the tests.

The FIFO is fully functional and used in many successful projects.

Usage

RTL sources are present in RTL folder under three flavors:

• rtl/async_fifo.v: a basic asynchronous dual-clock FIFO
• rtl/async_bidir_fifo.v: two instance of the first one into a single top level for full-duplex channel
• rtl/async_bidir_ramif_fifo.v: same than previous but with external RAM

The three FIFOs have a list file to get the associated fileset.

The testbench in sim/ provides an example about the instance and the configuration.

All three top levels have the same parameters:

• DSIZE: the size in bits of the datapath
• ASIZE: the size in bits of the internal RAM address bus. This implies the FIFO can be configured only with power of 2 depth
• FALLTHROUGH: allow to reduce the inner latency and propagate faster the data through the FIFO

License

Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. imitations under the License.

async_fifo's Issues

[feature-request] User define early full/ empty signal

Hello Damien Pretet,

First of all, thank you very much for your async-fifo project! I have been using it recently in my undergraduate senior design.

While looking through the verilog code of how awfull and arempty signal are generate, it seems to me that the only difference between how wfull and awfull is the 1'b1 offset.

However, for my application, I would like to have a wire signal that signals 4096 bit ahead of rempty. Thus, I wonder would it be possible and does not cause any problem to implement the feature of letting user pass a parameter at , then replace the 1'b1 offset with the value of the parameter that user-defined?

script missing

where is svutRun.py script?

Address width parameter on sync_x blocks not passed through from toplevel

Hi,

I've just tried using your block on the issue01 branch and have noticed that the address width parameter inside the sync_r2w and sync_w2r blocks is not specified on the their instance in async_fifo.v, meaning if you change the parameter on the instance of an async_fifo instance then it doesn't propagate down and causes the block to issue a lot of Xes.

It's also inconsistently named in those sync modules versus the others (ADDRSIZE vs ASIZE).

Thanks.

Potential BUG: In consistent awfull and arempty signal

I haven't tried to produce this in simulation yet. I will try to do it when I am free

During testing and usage, I found something interesting.

ASIZE = 13, DSIZE = 16,AWFULLSIZE = 4096 // half of the buffer

To test the correctness of my FIFO logic, I have my FPGA setup to be in a FIFO stream-in-out testing mode.

The Verilog will first read 4096 DSIZE data from the FIFO interface provided by Cypress FX3 and then write the data back to the host laptop.

After the 4096 DSIZE read, I assert the awful flag, which should be true since I am at half of the FIFO and AWFULLSIZE == 4096.
If Awfull is true, I will move to the next state to write the data back to the host laptop. But if awfull is not true, the FPGA will enter into an error state.

At the actual testing, the awfull flag is asserted to be true at the first 2 iterations of 4096 fifo read & write. However, at the 3 iteration, the assertion statement failed!

After looking over the document of the async fifo implementation and comparing the changes that I made from the last merge, I realized the problem is AWFULLSIZE is not being bit width cast.

I was able to fix the issue of inconsistent awfull signal by making the modification to cast the parameter into wires of (ADDRESIZE+1), same size with wgraynext.

Note: after making the changes, it still passes the simulation test.

[feature-request] Almost full and almost empty signals

Hello Damien Pretet,

I've been using your fifo in one of my projects for the last two weeks and so far it has worked flawlessly. Thank you for your contribution to the open source world!

There is however a feature that your fifo doesn't have and which I would really like to see: almost full and almost empty signals, to know a clock-tick in advance if the fifo is going to be full or empty.

Would it be possible for you to add those kinds of signals?

Thank you!

Greetings,
Renze Nicolai

Which modules are synthesizable?

Thank you very much for this great project. I am using the module async_fifo.v in my project. In simulation everything is working as expected. On my actual hardware it is not working as expected. I just want to confirm, is the module async_fifo.v safe for synthesis? Do I need to do anything to the "FALLTHROUGH" parameter for synthesis?

I just want to make sure the problem is with my verilog and not with your project. Thanks for any response.