xdweiustc Goto Github PK

32-verilog-mini-projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

adaptive_clustering

A lightweight and accurate point cloud clustering method

async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

cgnl-network.pytorch

Compact Generalized Non-local Network (NIPS 2018)

cortexm0_soc

Cortex M0 based SoC

deeplearning-models

A collection of various deep learning architectures, models, and tips

digilent-xdc

A collection of Master XDC files for Digilent FPGA and Zynq boards.

e200_opensource

The Ultra-Low Power RISC Core

fft-dit-fpga

Verilog module for calculation of FFT.

jeecg-boot

基于代码生成器的JAVA快速开发平台，开源界“小普元”超越传统商业开发平台！前后端分离架构：SpringBoot 2.x，Ant Design&Vue，Mybatis-plus，Shiro，JWT。强大的代码生成器让前后端代码一键生成，无需写任何代码! 引领新开发模式(OnlineCoding-> 代码生成-> 手工MERGE)，帮助Java项目解决70%重复工作，让开发更关注业务逻辑，既能快速提高开发效率，帮助公司节省成本，同时又不失灵活性。

kaggle_titanic

the data and ipython notebook of my attempt to solve the kaggle titanic problem

pic

图片

python-pcl

Python bindings to the pointcloud library (pcl)

radix-2-fft

Verilog code for a circuit implementation of Radix-2 FFT

serial-communication-gui-program

PyQt, Serial Communication GUI Program, between 2 different hardwares

tdc

Verilog implementation of a tapped delay line TDC

tdc-1

A Time to Digital Converter (TDC) on a Xilinx Virtex 5 FPGA.

tifr_fpga_tdc

Time to Digital Converter on an FPGA

verilog-ethernet

Verilog Ethernet components for FPGA implementation

verilog-template