Topic: soc Goto Github

👇 Here are 364 public repositories matching this topic...

0x783kb / security-operation-book
soc,一些常见的安全检测规则及事件
User: 0x783kb
threat-hunting attck security security-operation soc

aeturrell / occupationcoder
soc,Given a job title and job description, the algorithm assigns a standard occupational classification (SOC) code to the job.
User: aeturrell
Home Page: https://occupationcoder.readthedocs.io/
python tf-idf vacancies soc jobs economics text-analysis

akechishiro / slides-talks
soc,My own cybersecurity research talks/slides
User: akechishiro
arm cybersecurity cybersecurity-education hardware iot security slides soc spi talks

aleksandarkostovic / riscy-soc
soc,Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
User: aleksandarkostovic
risc-v soc riscy-soc verilog

apertus-open-source-cinema / naps
soc,An experiment for building gateware for the axiom micro / beta using amaranth-hdl
Organization: apertus-open-source-cinema
Home Page: https://apertus-open-source-cinema.github.io/naps/intro.html
nmigen axiom-beta gateware video wavelet compression fpga python soc zynq

arm-university / introduction-to-soc-design-education-kit
soc,Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedded programs targeted at the microprocessor to control the peripherals
Organization: arm-university
system-on-chip soc arm-cortex-m0 fpga system-on-chip-design amba arm cmsis cortex-m hardware-designs

azerimaker / penguino-stm32wl-lora-e5
soc,This repo contains all the necessary design and fabrication files for the Seeed Studio LoRa-E5 based Penguino Feather breakout board.
User: azerimaker
Home Page: https://makertronika.com/
lora lorawan stm32wl penguino adafruit feather lora-e5 soc

bank-of-england / occupationcoder
soc,Given a job title and job description, the algorithm assigns a standard occupational classification (SOC) code to the job.
Organization: bank-of-england
python tf-idf vacancies soc jobs economics text-analysis bankofengland boe

controlcompass / controlcompass.github.io
soc,Pointing cybersecurity teams to thousands of detection rules and offensive security tests aligned with common attacker techniques
User: controlcompass
Home Page: https://controlcompass.github.io
security intelligence cybersecurity threat-intelligence threat-hunting red-teaming red-team detection detection-engineering mitre-attack

cyb3rxp / awesome-soc
soc,A collection of sources of documentation, as well as field best practices, to build/run a SOC
User: cyb3rxp
cert csirt detection soc siem sirp soa soar tip architecture

deepfence / packetstreamer
soc,:star: :star: Distributed tcpdump for cloud native environments :star: :star:
Organization: deepfence
forensics-tools hacktoberfest infosectools network-analysis observability packet-capture packet-sniffer pcap secops security-tools snort soc suricata tcpdump-like traffic-monitoring zeek

dpretet / axi-crossbar
soc,An AXI4 crossbar implementation in SystemVerilog
User: dpretet
axi4 axi4-lite axi4-protocol axi4-full crossbar interconnect fpga fpga-soc processor asic-design

eshlomo1 / microsoft-sentinel-secops
soc,Microsoft Sentinel SOC Operations
User: eshlomo1
azure-sentinel security secops siem soc azure hunting ir incident-response microsoft

firesim / firechip
soc,Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.
Organization: firesim
rocket-chip soc risc-v

gem5-graphics / gem5-graphics
soc,gem5 simulator with a gpgpu+graphics GPU model
Organization: gem5-graphics
gpu graphics simulation android soc architecture gpgpu

jasonfreelab / histblinuxv100r005c00spc050
soc,Hisilicon SDK for SoC Hi3798Mv100 / Hi3798Cv200 / Hi3798Mv200 / Hi3798Mv300.
User: jasonfreelab
hi3798m hi3798mv200 kernel sdk soc hi3798mv100 hi3798mv300 hi3798cv200

mit-ll / cep
soc,The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.
Organization: mit-ll
riscv verilog risc-v fpga rocket-chip osh oshw soc chipyard

mthcht / awesome-lists
soc,Security lists for SOC detections
User: mthcht
blueteam hacktools keywords list offensive-security purpleteam redteam security soc awesome

mthcht / purpleteam
soc,Purpleteam scripts simulation & Detection - trigger events for SOC detections
User: mthcht
blueteam detection linux mitre-attack offensive-scripts purpleteam redteam security siem simulation

mthcht / threathunting-keywords
soc,Awesome list of keywords and artifacts for Threat Hunting sessions
User: mthcht
Home Page: https://mthcht.github.io/ThreatHunting-Keywords/
awesome-list blueteam detection-engineering endpoint-security iocs offensive-scripts offensive-security redteam siem soc

nusmodifications / nus-scripts
soc,Scripts to make life as an NUS student better and easier.
Organization: nusmodifications
nus scripts claims ta soc computing

patrowl / patrowlhears
soc,PatrowlHears - Vulnerability Intelligence Center / Exploits
Organization: patrowl
Home Page: https://patrowlhears.io
soc vulnerabilities vulnerability-detection exploits exploits-scripts automation patrowl threat threat-intelligence threatintel

rggen / rggen
soc,Code generation tool for control and status registers
Organization: rggen
verilog systemverilog uvm rtl ral csr soc fpga asic register-descriptions uvm-ral-model wiki-documents amba axi apb uvm-register-model eda vhdl wishbone-bus

riscv-mcu / e203_hbirdv2
soc,The Ultra-Low Power RISC-V Core
Organization: riscv-mcu
Home Page: https://doc.nucleisys.com/hbirdv2
risc-v riscv fpga hummingbird nuclei soc e203 china verilog low-power

satan1a / theroadofso
soc,学习安全运营的记录 | The knowledge base of security operation
User: satan1a
Home Page: https://wiki.y1ng.org
security-operations cybersecurity security-analysis threat-analysis security-operation soc wiki knowledge-base

saurabhshri / gsoc-2017-accepted-proposals
soc,Contains information about accepted GSoC 2017 Projects across various organizations along with the proposals.
User: saurabhshri
foss google-summer-of-code gsoc gsoc-2017 open-source proposal soc

securityjoes / forensicminer
soc,A really good DFIR automation for collecting and analyzing evidence designed for cybersecurity professionals.
Organization: securityjoes
Home Page: http://github.com/YosfanEilay
automation cortex crowdstrike cyber dfir edr fast forensics ir mdr powershell security soc xdr

securityjoes / masterparser
soc,MasterParser is a powerful DFIR tool designed for analyzing and parsing Linux logs
Organization: securityjoes
Home Page: https://github.com/YosfanEilay
dfir dfir-automation infosec ir mdr soc cyber-security powershell reporting tools automation digital-forensic incident-response cyber security

sergeykhbr / riscv_vhdl
soc,Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
User: sergeykhbr
Home Page: http://sergeykhbr.github.io/riscv_vhdl/
riscv soc vhdl simulator systemc qt cpu debugger

spinalhdl / saxonsoc
soc,SoC based on VexRiscv and ICE40 UP5K
Organization: spinalhdl
soc riscv rtl

spinalhdl / vexriscv
soc,A FPGA friendly 32 bit RISC-V CPU implementation
Organization: spinalhdl
cpu fpga riscv soc softcore spinalhdl verilog vhdl

staok / arm-linux-study
soc,ARM Linux 的学习历程。包括应用、驱动、设备树，GCC, Make, CMake, Bash, Vim, Git 等等大集合内容。文章遵守 CC BY NC SA 4.0 协议。
User: staok
arm bash cmake driver-programming dts gcc linux make makefile soc vim

stnolting / neo430
soc,:computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
User: stnolting
vhdl fpga soft-core microcontroller msp430 gcc customizable processor soc system-on-chip

stnolting / neorv32
soc,:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
User: stnolting
Home Page: https://neorv32.org
risc-v soft-core vhdl fpga soc microcontroller processor cpu riscv system-on-chip

stnolting / neorv32-setups
soc,📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
User: stnolting
Home Page: https://github.com/stnolting/neorv32
neorv32 fpga xilinx intel lattice ghdl yosys soc risc-v vhdl

strath-sdr / rfsoc-book
soc,Companion Jupyter Notebooks for the RFSoC-Book.
Organization: strath-sdr
Home Page: https://www.rfsocbook.com/
fpga jupyter pynq rfsoc soc

tenzir / tenzir
soc,Open source security data pipelines.
Organization: tenzir
Home Page: https://docs.tenzir.com
incident-response threathunting siem soc security dataops investigation pcap secdataops netflow

theresafewconors / sooty
soc,The SOC Analysts all-in-one CLI tool to automate and speed up workflow.
User: theresafewconors
python soc security security-automation analysts automation reputation-check urlscan proofpoint-decoder phishing

tonyphipps / meerkat
soc,A collection of PowerShell modules designed for artifact gathering and reconnaisance of Windows-based endpoints.
User: tonyphipps
threat hunt red blue purple team incident response baseline monitor

tonyphipps / siem
soc,SIEM Tactics, Techiques, and Procedures
User: tonyphipps
threat hunt red blue purple team incident response baseline monitor

trellix-enterprise / rts-queries
soc,Practical Orientation Of MVISION EDR Query Language
Organization: trellix-enterprise
mvision-edr mvision rts real-time-search edr hunting collectors soc blue-team

ucb-bar / chipyard
soc,An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Organization: ucb-bar
Home Page: https://chipyard.readthedocs.io/en/stable/
rocket-chip chip-generator chisel riscv rtl soc peripherals chipyard risc-v boom

ucb-bar / constellation
soc,A Chisel RTL generator for network-on-chip interconnects
Organization: ucb-bar
Home Page: http://constellation.readthedocs.io
chisel hardware interconnect network-on-chip noc rtl soc

ui-model / ui-model
soc,UI Model major repository
Organization: ui-model
Home Page: http://ui-model.com
ui-model reuse library soc angular react no-comonent

viralmaniar / ddwpasterecon
soc,DDWPasteRecon tool will help you identify code leak, sensitive files, plaintext passwords, password hashes. It also allow member of SOC & Blue Team to gain situational awareness of the organisation's web exposure on the pastesites. It Utilises Google's indexing of pastesites to gain targeted intelligence of the organisation. Blue & SOC teams can collect and analyse data from these indexed pastesites to better protect against unknown threats.
User: viralmaniar
darkweb darkweb-hacking ddw attacksurface threat-intelligence threat-hunting threat-sharing iocs pastesites reconnaissance

wangxuan95 / ustc-rvsoc
soc,An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
User: wangxuan95
Home Page: https://gitee.com/wangxuan95/USTC-RVSoC
riscv risc-v rv32i soc fpga softcore rtl verilog systemverilog cpu

waynezv / fpga_ultrasound
soc, CMU 18545 FPGA project -- Multi-channel ultrasound data acquisition and beamforming system.
User: waynezv
fpga soc data-acquisition ultrasound beamforming

wilsonchen003 / hdlgen
soc,HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
User: wilsonchen003
automation hdl perl python script verilog asic soc rtl

xboot / xboot
soc,The extensible bootloader for embedded system with application engine, write once, run everywhere.
Organization: xboot
Home Page: https://xboot.github.io
xboot bootloader lua application-engine embedded-systems soc samsung rockchip allwinner freescale mtk operating-system boot os

xilinx / vitis_accel_examples
soc,Vitis_Accel_Examples
Organization: xilinx
Home Page: http://xilinx.github.io/Vitis_Accel_Examples/
vitis xilinx alveo zynq fpga-programming soc acap