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Vitis_Accel_Examples

Home Page: http://xilinx.github.io/Vitis_Accel_Examples/

License: MIT License

C++ 24.89% Makefile 28.47% C 0.32% Shell 0.79% Python 13.41% Tcl 3.49% Verilog 10.16% SystemVerilog 18.22% Perl 0.26%

vitis xilinx alveo zynq fpga-programming soc acap

vitis_accel_examples's Introduction

Vitis™ Data Center Acceleration Examples

Welcome to the Vitis Data Center Acceleration Examples repository. This repository contains examples to showcase various features of the Vitis™ tools targeting Alveo Data Center platforms. It is expected that users have gone through the Vitis HLS Introductory Examples and Vitis Tutorials and have developed a basic understanding of the tools and the programming model. This repository illustrates specific scenarios related to host code and kernel programming through small working examples. The intention is for users to be able to use these working examples as a reference while developing their own accelerator application based on AMD Alveo platforms.

Brief description of the examples

Example	Description
host_xrt	XRT Native APIs examples for optimal host-kernel interaction with AMD Devices
performance	Examples that cover performance related aspects for kernel-to-memory, host-to-kernel and host-to-memory
rtl_kernels	RTL Kernels based examples covering mix of RTL and HLS C++ kernels and hardware debug in Vitis flow
sys_opt	Examples covering multiple devices, multiple processes and kernel swap use cases

For more comprehensive documentation,

^{Terms and Conditions}

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vitis_accel_examples's Issues

example "hello_world"

Has anyone gone through the "hello_world" example under "VITIS_Accel_examples"?Will you share your steps?

../src/host.hpp invokes:
#include "xcl2.hpp"
#include
#include
#define DATA_SIZE 4096

and xcl2.hpp invokes:
#include <CL/cl2.hpp>
#include <CL/cl_ext_xilinx.h>
I can not find cl2.hpp ,cl_ext_xilinx.h.

Streaming Example ( K2K) for Xilinx Vitis

Is there an example similar to streaming_k2k_mm for the cpp kernels because Xilinx Vitis shows error while running the same example ( as it is ) . The following error comes

ERROR: [v++ 17-1309] Gcc: /tools/reconfig/xilinx/Vitis/2020.1/Vitis/2020.1/bin/../data/emulation/include/xcl_top_defines.h:57:request for member ‘empty’ in ‘* rStream’, which is of non-class type ‘int’
ERROR: [v++ 17-1309] Gcc: /tools/reconfig/xilinx/Vitis/2020.1/Vitis/2020.1/bin/../data/emulation/include/xcl_top_defines.h:58:request for member ‘read’ in ‘* rStream’, which is of non-class type ‘int’

Resource utilization: RAMB18 and RAMB36/FIFO over-utilized in Pblock pblock_dynamic_region

Hello,
I am trying to compile the array_partition example with size modified to 1024x1024 matrix multiplication with Vitis 2020.1 software for Alveo U200 board. I got the following error during the compilation for hardware:

===>The following messages were generated while processing /data/master/Vitis_Accel_Examples/cpp_kernels/array_partition/build/link/vivado/vpl/prj/prj.runs/impl_1 :
ERROR: [VPL UTLZ-1] Resource utilization: RAMB18 and RAMB36/FIFO over-utilized in Pblock pblock_dynamic_region (This design requires more RAMB18 and RAMB36/FIFO cells than are available in Pblock 'pblock_dynamic_region'. This design requires 10656 of such cell types but only 3696 compatible sites are available in Pblock 'pblock_dynamic_region'. Please consider increasing the span of Pblock 'pblock_dynamic_region' or removing cells from it.)
ERROR: [VPL UTLZ-1] Resource utilization: RAMB18 and RAMB36/FIFO over-utilized in Top Level Design (This design requires more RAMB18 and RAMB36/FIFO cells than are available in the target device. This design requires 11296 of such cell types but only 4320 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)
ERROR: [VPL UTLZ-1] Resource utilization: RAMB36/FIFO over-utilized in Pblock pblock_dynamic_region (This design requires more RAMB36/FIFO cells than are available in Pblock 'pblock_dynamic_region'. This design requires 5328 of such cell types but only 1848 compatible sites are available in Pblock 'pblock_dynamic_region'. Please consider increasing the span of Pblock 'pblock_dynamic_region' or removing cells from it.)
ERROR: [VPL UTLZ-1] Resource utilization: RAMB36/FIFO over-utilized in Top Level Design (This design requires more RAMB36/FIFO cells than are available in the target device. This design requires 5639 of such cell types but only 2160 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)
ERROR: [VPL UTLZ-1] Resource utilization: RAMB36E2 over-utilized in Pblock pblock_dynamic_region (This design requires more RAMB36E2 cells than are available in Pblock 'pblock_dynamic_region'. This design requires 5328 of such cell types but only 1848 compatible sites are available in Pblock 'pblock_dynamic_region'. Please consider increasing the span of Pblock 'pblock_dynamic_region' or removing cells from it.)
ERROR: [VPL UTLZ-1] Resource utilization: RAMB36E2 over-utilized in Top Level Design (This design requires more RAMB36E2 cells than are available in the target device. This design requires 5639 of such cell types but only 2160 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)
ERROR: [VPL 4-23] Error(s) found during DRC. Placer not run.
ERROR: [VPL 60-773] In '/data/master/Vitis_Accel_Examples/cpp_kernels/array_partition/build/link/vivado/vpl/runme.log', caught Tcl error:  problem implementing dynamic region, impl_1: place_design ERROR, please look at the run log file '/data/master/Vitis_Accel_Examples/cpp_kernels/array_partition/build/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
WARNING: [VPL 60-732] Link warning: No monitor points found for BD automation.
WARNING: [VPL 60-732] Link warning: The available BRAMs may not be sufficient to accommodate the kernels
ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, impl_1: place_design ERROR, please look at the run log file '/data/master/Vitis_Accel_Examples/cpp_kernels/array_partition/build/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
ERROR: [VPL 60-1328] Vpl run 'vpl' failed
ERROR: [VPL 60-806] Failed to finish platform linker
INFO: [v++ 60-1442] [10:55:44] Run run_link: Step vpl: Failed
Time (s): cpu = 00:00:45 ; elapsed = 01:09:52 . Memory (MB): peak = 1323.551 ; gain = 0.000 ; free physical = 38381 ; free virtual = 177854
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
INFO: [v++ 60-1653] Closing dispatch client.
Makefile:118: recipe for target 'build//matmul.xclbin' failed
make: *** [build//matmul.xclbin] Error 1
nimbix@JARVICENAE-0A0A1849:~/data/master/Vitis_Accel_Examples/cpp_kernels/array_partition$

what could be the possible solution for this issue ?
Thank you!

Issue in SLR - assign

In this https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/sys_opt/slr_assign
after generating binary, I just verified binary with vitis_analyser. Both the kernels assigned in bank1.

Expected response - vmult to SLR0, vadd to SLR1

Please let me know, what will be the issue.
Thanks

When use GDB out put error

Hi,

I have run the Vitis_Accel_Example such as this code

And I want to know more informations about the function enqueueMigrateMemObjects

However, no matter the Vitis compiler is used to debug the code, or GDB is used to debug the code from the command line, but the final error will be reported.

Error notification in VItis is Can't find a source file at "/opt/xrt/src/runtime_src/xdp/appdebug/appdebug.cpp"

And Error notification in GDB is

__gnu_cxx::new_allocator<cl::Memory>::deallocate (this=<optimized out>, __p=<optimized out>) at /usr/include/c++/5/ext/new_allocator.h:110
110	      { ::operator delete(__p); }
(gdb) 
0x00007ffff77b3f10 in operator delete(void*) () from /usr/lib/x86_64-linux-gnu/libstdc++.so.6
(gdb) 
Single stepping until exit from function _ZdlPv,
which has no line number information.
__GI___libc_free (mem=0x63c0d0) at malloc.c:2941
2941	malloc.c: No such file or directory.

How do I debug to find the correct function call flow?

By the way, My Vitis IDE version is v2020.2.0(64.bit). And XRT version is 2020.2 and my System is Ubuntu 16.04, kernel version is 5.1.0.

Thank, hundan

Issues booting sw_emu tftp

Hi there...

I've been trying to get the hello world example to work in vitis 2019 the past day or so. I've ended up finding that these instructions here had a lot of the necessary background that helped getting started. (I'd like to suggest that something with this level of detail gets pulled into this readme for xilinx noobs like myself.)

https://www.hackster.io/news/vivado-vitis-2019-2-install-on-ubuntu-18-04-lts-93242be6c9eb

One issue I'm stumped on is how to get my xilinx project to put its output into my hosts /tftpboot directory. I have a tftpserver configured on my ubuntu linux host, and I have a /tftpboot which I believe is set with correct permissions.

I found here on page 62 https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug1144-petalinux-tools-reference-guide.pdf that there's a petalinux-config command that should allow me to set a Copy final images to tftpboot checkbox, but when I run petalinux-config within the hello_world example's folder on my host, I get an error that I am not inside a PetaLinux project.

I tried running petalinux-config also from the application project that I created from the hello_world template from within the 2019.2 IDE. Any ideas?

Thanks,

Makefile issue for embedded platforms

The Makefile for the non-x86 builds does not include the VPP_LDFLAGS_vadd variable. Therefore the xclbin does not include 4 CUs.

Vitis_Accel_Examples/sys_opt/advanced_config has two clock setup?

in the 1st config file (used for kernel compile): https://github.com/Xilinx/Vitis_Accel_Examples/blob/master/sys_opt/advanced_config/vadd_vadd.ini
kernel_frequency=0:150
[advanced]
prop=solution.hls_pre_tcl=my_directives.tcl
in 2nd config file(used for linker): https://github.com/Xilinx/Vitis_Accel_Examples/blob/master/sys_opt/advanced_config/vadd.ini
kernel_frequency=0:280

Is this correct config? If it does, which clock will be the target clock?

Systolic Array Error: unsupported memory access on variable 'a'

Hello,
I am trying to run the systolic_array example but I am getting the following error message during the sw_emulation.
I haven't modified the code so it's the default one provided with the project
What could be the reason behind this error ?
Thank you!

===>The following messages were generated while  performing high-level synthesis for kernel: mmult Log file: /projects/Vitis_Accel_Examples/cpp_kernels/systolic_array/_x.hw.xilinx_u200_xdma_201830_2/mmult/mmult/vivado_hls.log :
INFO: [v++ 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
ERROR: [v++ 200-61] /projects/Vitis_Accel_Examples/cpp_kernels/systolic_array/src/mmult.cpp:113: unsupported memory access on variable 'a' which is (or contains) an array with unknown size at compile time.
ERROR: [v++ 200-70] Synthesizability check failed.
ERROR: [v++ 60-300] Failed to build kernel(ip) mmult, see log for details: /projects/Vitis_Accel_Examples/cpp_kernels/systolic_array/_x.hw.xilinx_u200_xdma_201830_2/mmult/mmult/vivado_hls.log
ERROR: [v++ 60-599] Kernel compilation failed to complete
ERROR: [v++ 60-592] Failed to finish compilation
Makefile:104: recipe for target '_x.hw.xilinx_u200_xdma_201830_2/mmult.xo' failed
make: *** [_x.hw.xilinx_u200_xdma_201830_2/mmult.xo] Error 1

XRT stream example cannot achieve expected PCIe bandwidth

Hi,

I am following this example: https://github.com/Xilinx/Vitis_Accel_Examples/tree/2020.1/host/streaming_host_bandwidth. The FPGA platform is xilinx_u250_qdma_201920_1.

I changed the example a bit to profile the XRT stream read throughput. The modified kernel reads from the input FIFO, and when the EOS signal arrives, the kernel writes to the output FIFO once and exits. Here is the profiling result I got by changing the input data size:

The H2C single XRT stream channel can only achieve up to 7-ish GB/s when the data size is smaller than 2GB. If I increase the transfer data size further (e.g. to 4GB), then I am able to achieve around 14-ish GB/s throughput.

But from this report (https://www.xilinx.com/Attachment/Xilinx_Answer_71453_QDMA_Performance_v5.pdf) page 12, the H2C single queue design should be able to achieve TH=100Gbps with a much smaller data size (e.g. around 1KiB).

My guess is that some set-up overheads are included in the measured runtime, so the throughput is affected as a result. Is there any way to measure these unrelated overhead? Or am I using the XRT stream in a wrong way?

Also another question, does a single XRT stream channel maps to a QDMA queue by default? for HLS programmer, how do I configure the number of queues used in my design?

Your help will be highly appreciated.

host/streaming_host_bandwidth non-blocking fails and hangs

Hi,

As I am trying the host-kernel streaming examples, I found that make run TARGET=hw DEVICE=xilinx_u200_qdma_201920_1 in host/streaming_host_bandwidth fails and hangs with the following output:

./streaming_host_bandwidth ./build_dir.hw.xilinx_u200_qdma_201920_1/krnl_stream_adder1.xclbin
Vector Increment of elements 0x10000000 by 1 
Found Platform
Platform Name: Xilinx
INFO: Reading ./build_dir.hw.xilinx_u200_qdma_201920_1/krnl_stream_adder1.xclbin
Loading: './build_dir.hw.xilinx_u200_qdma_201920_1/krnl_stream_adder1.xclbin'
Trying to program device[0]: xilinx_u280_xdma_201920_3
XRT build version: 2.8.726
Build hash: 7c93966ead2dec777b92bdc379893f22b5bd561e
Build date: 2020-11-11 20:29:19
Git branch: 2020.2
PID: 1234
UID: 1000
[Mon Dec 21 06:59:04 2020 GMT]
HOST: foo
EXE: /path/to/Vitis_Accel_Examples/host/streaming_host_bandwidth/streaming_host_bandwidth
[XRT] ERROR: Xclbin does not match shell on card.
[XRT] ERROR: Shell VBNV is 'xilinx_u280_xdma_201920_3'
[XRT] ERROR: Xclbin VBNV is 'xilinx_u200_qdma_201920_1'
[XRT] ERROR: Use 'xbmgmt flash' to update shell.
[XRT] ERROR: See dmesg log for details. err=-95
[XRT] ERROR: Failed to load xclbin.
Failed to program device[0] with xclbin file!
Trying to program device[1]: xilinx_u250_xdma_201830_2
[XRT] ERROR: Xclbin does not match shell on card.
[XRT] ERROR: Shell VBNV is 'xilinx_u250_xdma_201830_2'
[XRT] ERROR: Xclbin VBNV is 'xilinx_u200_qdma_201920_1'
[XRT] ERROR: Use 'xbmgmt flash' to update shell.
[XRT] ERROR: See dmesg log for details. err=-95
[XRT] ERROR: Failed to load xclbin.
Failed to program device[1] with xclbin file!
Trying to program device[2]: xilinx_u50_gen3x16_xdma_201920_3
[XRT] ERROR: Xclbin does not match shell on card.
[XRT] ERROR: Shell VBNV is 'xilinx_u50_gen3x16_xdma_201920_3'
[XRT] ERROR: Xclbin VBNV is 'xilinx_u200_qdma_201920_1'
[XRT] ERROR: Use 'xbmgmt flash' to update shell.
[XRT] ERROR: See dmesg log for details. err=-95
[XRT] ERROR: Failed to load xclbin.
Failed to program device[2] with xclbin file!
Trying to program device[3]: xilinx_u200_qdma_201920_1
Device[3]: program successful!
############################################################
                     Blocking Stream                        
############################################################
[ Case: 1 ] -> Throughput = 6.7537 GB/s
TEST PASSED
############################################################
                  Non-Blocking Stream                       
############################################################
[XRT] ERROR: xclWriteQueue: NONBLOCK but aio NOT enabled.

[XRT] ERROR: xclReadQueue: NONBLOCK but aio NOT enabled.

[XRT] ERROR: xclPollCompletion: async io is not enabled
[XRT] ERROR: sync io is not enabled
src/host.cpp:249 Error calling xcl::Stream::pollStreams(device.get(), poll_req, 2, 2, &num_compl, 50000, &ret), error code is: -30
[XRT] WARNING: Profiling may contain incomplete information. Please ensure all OpenCL objects are released by your host code (e.g., clReleaseProgram()).

Output from xbutil scan:

INFO: Found total 4 card(s), 4 are usable
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
System Configuration
OS name:	Linux
Release:	4.15.0-128-generic
Version:	#131-Ubuntu SMP Wed Dec 9 06:57:35 UTC 2020
Machine:	x86_64
Model:		PowerEdge R740
CPU cores:	32
Memory:		95127 MB
Glibc:		2.27
Distribution:	Ubuntu 18.04.4 LTS
Now:		Mon Dec 21 06:50:32 2020 GMT
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
XRT Information
Version:	2.8.726
Git Hash:	7c93966ead2dec777b92bdc379893f22b5bd561e
Git Branch:	2020.2
Build Date:	2020-11-11 20:29:19
XOCL:		2.8.726,7c93966ead2dec777b92bdc379893f22b5bd561e
XCLMGMT:	2.8.726,7c93966ead2dec777b92bdc379893f22b5bd561e
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 [0] 0000:d8:00.1 xilinx_u280_xdma_201920_3(ID=0x5e278820) user(inst=131)
 [1] 0000:af:00.1 xilinx_u250_xdma_201830_2(ID=0x5d14fbe6) user(inst=130)
 [2] 0000:5e:00.1 xilinx_u50_gen3x16_xdma_201920_3 user(inst=129)
 [3] 0000:3b:00.1 xilinx_u200_qdma_201920_1(ID=0x5dccb0ca) user(inst=128)

Did I miss any system configuration? Any suggestions would be helpful. Thank you!

Cannot run v++ inside python subprocess

I tried to run the v++ compilation inside a python subprocess. but I got the following error

INFO: [CF2BD 82-28] cf2xd finished successfully
INFO: [CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -bd pfm_dynamic.bd -dn dr -dp /work/shared/users/phd/sx233/uptune-1/samples/vivado/build_dir.hw.xilinx_u280_xdma_201920_1/link/sys_link/_sysl/.xsd

rlwrap: Oops, crashed (caught SIGFPE) - this should not have happened!
If you need a core dump, re-configure with --enable-debug and rebuild
Resetting terminal and cleaning up...
ERROR: [CF2BD 82-34] cf_xsd: Failed to generate design file: dr.bd.tclERROR: [SYSTEM_LINK 82-36] [22:38:20] cf2bd failed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 285.742 ; gain = 0.000 ; free physical = 267708 ; free virtual = 360850
ERROR: [SYSTEM_LINK 82-61] Error generating design file dr.bd.tcl
ERROR: [SYSTEM_LINK 82-80] Unable to create top-level block diagram
INFO: [v++ 60-1442] [22:38:20] Run run_link: Step system_link: FailedTime (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 689.844 ; gain = 0.000 ; free physical = 267726 ; free virtual = 360868
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
make: *** [Makefile:104: build_dir.hw.xilinx_u280_xdma_201920_1/kernel.xclbin] Error 1

Is there a way to launch multiple Vitis compilation tasks (where the std.input and std.out are redirected) without breaking the tool flow?

Errors when running software emulation on Vitis_Accel_Examples/host_xrt/hbm_simple_xrt

Building the code with my Vitis IDE using software emulation gives no error.
But running it gives the error message in the following.
I use all the default building configuration from this repo and Vitis IDE.
My target platform is xilinx_u50_gen3x16_xdma_201920_3.
Please help me out. Thanks a lot.

Open the device0
Load the xclbin /home/edci/vitis_workspace/HBM_XRT_system/Emulation-SW/krnl_vadd.xclbin
Running CASE 1  : Single HBM for all three Buffers 
input 1 -> bank 0 
input 2 -> bank 0 
output  -> bank 0 
Allocate Buffer in Global Memory
synchronize input buffer data to device global memory
Execution of the kernel
Get the output data from the device
[CASE 1] THROUGHPUT = 1.68053 GB/s
Running CASE 2: Three Separate Banks for Three Buffers
input 1 -> bank 1 
input 2 -> bank 2 
output  -> bank 3 
Allocate Buffer in Global Memory
synchronize input buffer data to device global memory
Execution of the kernel
terminate called after throwing an instance of 'std::runtime_error'
  what():  No compute units satisfy requested connectivity

hello_world/Makefile:151 has not declare "$(B_NAME)"

When I in the directory hello_world and try to compile use the options below:

make all \
        TARGET=sw_emu \
        DEVICE=zcu102_base \
        HOST_ARCH=aarch64 \
        SYSROOT=/opt/petalinux/2019.2/sysroots/aarch64-xilinx-linux/

This Command will make an error because the $(B_NAME) is not declare in the Makefile at 151 line.
It causes wrong path, and I try to change it to the right path of my sysroots, then the Makefile works correctly.

hello_world/Makefile

I found a few issues while running commands using make

1)make build is not working
2)make all reports error for HOST_ARCH= aarch64

fatal error: CL/cl2.hpp: No such file or directory
#include <CL/cl2.hpp>
^~~~~~~~~~~~

aie_adder fails to compile

Trying to compile aie_adder fails:

Work/ps/c_rts/aie_control_xrt.cpp:1:10: fatal error: iostream: No such file or directory
    1 | #include <iostream>
      |          ^~~~~~~~~~
compilation terminated.

Adding a symlink of sdk on xilinx-versal-common top level directory also does not help.
The iostream is part of the /usr/include/c++/10.02 .

Why is the Makefile not picking this up?

Xilinx vitis HW emulation exception caught error

I have been trying to solve this error for over a month but no results every time I run the HW emu gives this error . the software emulation runs fine but don't know what's the problem with the hardware . the memory also is not that much allocated just a matrix of 32*32.

[XRT] WARNING: Profiling may contain incomplete information. Please ensure all OpenCL objects are released by your host code (e.g., clReleaseProgram()).
ERROR: [EMU 60-601] Exception Caught - Failed with the command REMOVE operation at the Line Number: 1394
Makefile:135: recipe for target 'check' failed
make: *** [check] Error 1

Cpp_kernels/Systolic_Array: large runtime and excessive memory usage problem

Hello,
I was trying to tune the size of the systolic array example (Default 16x16 matrix multiplication) I changed the DATA_SIZE and MAX_SIZE to 256 in host.cpp file and I changed the MAX_SIZE in mmult.cpp to 256 too. The sw_emu gave me correct results and showed that TEST PASSED but when I tried to the hw part it gave me the following error:

===>The following messages were generated while performing high-level synthesis for kernel: mmult Log file: /projects/Vitis_Accel_Examples/cpp_kernels/systolic_array256/_x.hw.xilinx_u200_xdma_201830_2/mmult/mmult/vivado_hls.log : INFO: [v++ 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints. ERROR: [v++ 203-504] Stop unrolling loop 'systolic2' (/projects/Vitis_Accel_Examples/cpp_kernels/systolic_array256/src/mmult.cpp:183) in function 'mmult' because it may cause large runtime and excessive memory usage due to increase in code size. Please avoid unrolling the loop or form sub-functions for code in the loop body. ERROR: [v++ 200-70] Pre-synthesis failed. ERROR: [v++ 60-300] Failed to build kernel(ip) mmult, see log for details: /projects/Vitis_Accel_Examples/cpp_kernels/systolic_array256/_x.hw.xilinx_u200_xdma_201830_2/mmult/mmult/vivado_hls.log ERROR: [v++ 60-599] Kernel compilation failed to complete ERROR: [v++ 60-592] Failed to finish compilation Makefile:97: recipe for target '_x.hw.xilinx_u200_xdma_201830_2/mmult.xo' failed make: *** [_x.hw.xilinx_u200_xdma_201830_2/mmult.xo] Error 1

So I changed the MAX_SIZE of mmult.cpp to 128,64,32,16 and in all cases the calculation results of FPGA didn't match to the CPU results. What could be the ideal solution for this issue ? The line 183 in mmult corresponds to the systolic2: part

Thank you in advance

Printing variables inside kernel

Hi All

I have been trying to debug my kernel ( as during Software emulation it is giving errors ) so inorder to debug I wanted to print variable inside my kernel and check its value .

I have already checked the documentation, it says to use the printf function but when I used it it said undefined function and when I added the file stdio.h ( which contains the printf definition ) it said file not found.

Is there any way to print the variables inside the kernel.

Thanks in advance.

multiple different kernels running on the Alevo card

excuse me, has anyone done a similar project using vitis ?
i want to make an application project about muti_different kernels on the Alevo card.
i hve tried to make it. it didn't show some errors about src. However, it failed to build Emulation-SW.
i don't know how to deal with it.
do you have some demo about this? thanks a lot.

v++ not able to synthesize the memory interface of top-level function

Hi,

I was trying to run the PLRAM example in the repo, and ran into some issues when compiling it with v++. When I compile the source directly, as https://github.com/Xilinx/Vitis_Accel_Examples/blob/master/cpp_kernels/plram_access/src/mmult.cpp#L45-L51, the tool first complains that the size of the input array is unknown, so I changed the top-level function signature as followed:

void mmult(const int a[64], // Read-Only Matrix A
           const int b[64], // Read-Only Matrix B
           int c[64],       // Output Result
           int a_row,    // Matrix A Row Size
           int a_col,    // Matrix A Col Size
           int b_col     // Matrix B Col Size
           ) {

After I changed the function, the v++ complains another issue:

===>The following messages were generated while  performing high-level synthesis for kernel: mmult Log file: /work/shared/users/phd/sx233/Vitis_Accel_Examples/cpp_kernels/plram_access/_x.hw.xilinx_u280_xdma_201920_1/mmult/mmult/vivado_hls.log :
INFO: [v++ 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [v++ 204-61] Pipelining loop 'readA'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'readB'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 204-61] Pipelining loop 'outer_loop1_outer_loop2_inner_loop'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 8.
INFO: [v++ 204-61] Pipelining loop 'writeC'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [v++ 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [v++ 200-789] **** Estimated Fmax: 309.02 MHz
ERROR: [v++ 213-400] This design has interfaces which are not supported by Vitis. Check interface pragmas to ensure the design only uses one s_axilite interface including the 'return' port and one or more m_axi interfaces with offset=slave set to the s_axilite interface; there should not be any other port interface used.
ERROR: [v++ 200-445] Unexpected error generating RTL model: generate_json error: Found incompatible interfaces
ERROR: [v++ 60-300] Failed to build kernel(ip) mmult, see log for details: /work/shared/users/Vitis_Accel_Examples/cpp_kernels/plram_access/_x.hw.xilinx_u280_xdma_201920_1/mmult/mmult/vivado_hls.log
ERROR: [v++ 60-599] Kernel compilation failed to complete
ERROR: [v++ 60-592] Failed to finish compilation
make: *** [_x.hw.xilinx_u280_xdma_201920_1/mmult.xo] Error 1

Example host/host_memory_simple (hw_emu) is not compiling

Is the following error due to installation problem or the example itself, it is example host/host_memory_simple?
It compiles for sw_emu but not hw_emu.

it says "platforminfo <platform.xpfm path> for sptag information" but there is no information about sptag

I am using all the latest stuff from Xilinx, Xilinx Unified Installer 2021.2 including the patch released 6 January.

$ uname -rs
Linux 5.4.0-21-generic

$ lsb_release -a
No LSB modules are available.
Distributor ID: Ubuntu
Description: Ubuntu 20.04 LTS
Release: 20.04
Codename: focal

HW: U50

----- Start: examples of working built ------
hello_world
make run TARGET=sw_emu PLATFORM=xilinx_u50_gen3x16_xdma_201920_3
TEST PASSED
make run TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_201920_3
TEST PASSED
make run TARGET=hw PLATFORM=xilinx_u50_gen3x16_xdma_201920_3
TEST PASSED

----- End: examples of working built ------

host/host_memory_simple
make run TARGET=sw_emu PLATFORM=xilinx_u50_gen3x16_xdma_201920_3
TEST PASSED

make run TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_201920_3

INFO: [CFGEN 83-0] Kernel Specs:
INFO: [CFGEN 83-0] kernel: krnl_vadd, num: 1 {krnl_vadd_1}
INFO: [CFGEN 83-0] Port Specs:
INFO: [CFGEN 83-0] kernel: krnl_vadd_1, k_port: m_axi_gmem, sptag: HOST[0]
ERROR: [CFGEN 83-2287] --sp tag applied with an invalid sp tag: HOST[0]
ERROR: [CFGEN 83-2297] Please consult platforminfo <platform.xpfm path> for sptag information
ERROR: [CFGEN 83-2298] Exiting due to previous error
ERROR: [SYSTEM_LINK 82-36] [16:20:26] cfgen failed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2169.344 ; gain = 0.000 ; free physical = 52644 ; free virtual = 94874
ERROR: [SYSTEM_LINK 82-62] Error generating design file for /home/zzzzzz/.Xilinx/Vitis/2021.2/vitis_examples/Vitis_Accel_Examples/host/host_memory_simple/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/link/sys_link/cfgraph/cfgen_cfgraph.xml, command: /tools/Xilinx/Vitis/2021.2/bin/cfgen -sp krnl_vadd_1.m_axi_gmem:HOST[0] -dmclkid 0 -r /home/zzzzzz/.Xilinx/Vitis/2021.2/vitis_examples/Vitis_Accel_Examples/host/host_memory_simple/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /home/zzzzzz/.Xilinx/Vitis/2021.2/vitis_examples/Vitis_Accel_Examples/host/host_memory_simple/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/link/sys_link/cfgraph/cfgen_cfgraph.xml
ERROR: [SYSTEM_LINK 82-96] Error applying explicit connections to the system connectivity graph
ERROR: [SYSTEM_LINK 82-79] Unable to create system connectivity graph
INFO: [v++ 60-1442] [16:20:26] Run run_link: Step system_link: Failed
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2063.574 ; gain = 0.000 ; free physical = 52681 ; free virtual = 94912
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
INFO: [v++ 60-1653] Closing dispatch client.
make: *** [Makefile:132: build_dir.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/krnl_vadd.xclbin] Error 1

Multiple versions of xcl2.hpp

Hello,
I am using the functions defined in xcl2.hpp and xcl2.cpp files in my host code for OpenCL accelerated kernel on a Xilinx platform.
However, I have noticed that multiple different versions of this file exist in this repository and also in the one for Vitis Libraries :
https://github.com/Xilinx/Vitis_Libraries
I am not sure that this is a real issue, but it seems weird enough to be asked.

Question: Which version of the header should I use? I also noticed that there is a dependency to "CL/cl_ext_xilinx.h" in some headers, so is "xcl2.hpp" platform- or version-dependent?

Here are the sha1sum of all xcl2.hpp found in this repository and in the one for Vitis Libraries :

[Vitis_Accel_Examples]find . -name "xcl2.hpp" | xargs -I {} sha1sum {}

3d923b533c2cab84fcee807dcda0cd290fc89fa1  ./library_examples/gemm/include/sw/xcl2/xcl2.hpp
71acdaeb2de97a706eeb827e4be2f60e2fdb5961  ./library_examples/MCEuropeanEngine/src/xcl2.hpp
35ee2824550aeead5ac1c8eec3e5d29a78490e08  ./library_examples/anti_money_laundering/host/xcl2.hpp
fd288f83104689f39542c9c23668fb9cfc5fef8d  ./library_examples/gzip_app/include/xcl2.hpp
964b7ad69b305ec1a825bb17e0df806b8903b888  ./common/includes/xcl2/xcl2.hpp


[Vitis_Libraries]find . -name "xcl2.hpp" | xargs -I {} sha1sum {}

38a7f4189b77621ae4dde50e1d27dd1f9fe04121  ./codec/ext/xcl2/xcl2.hpp
38a7f4189b77621ae4dde50e1d27dd1f9fe04121  ./database/ext/xcl2/xcl2.hpp
38a7f4189b77621ae4dde50e1d27dd1f9fe04121  ./dsp/ext/xcl2/xcl2.hpp
38a7f4189b77621ae4dde50e1d27dd1f9fe04121  ./utils/ext/xcl2/xcl2.hpp
38a7f4189b77621ae4dde50e1d27dd1f9fe04121  ./graph/ext/xcl2/xcl2.hpp
38a7f4189b77621ae4dde50e1d27dd1f9fe04121  ./security/ext/xcl2/xcl2.hpp
38a7f4189b77621ae4dde50e1d27dd1f9fe04121  ./solver/ext/xcl2/xcl2.hpp

c041215de4ef2a9012f78417901addeeb398f8ec  ./blas/L2/include/xcl2/xcl2.hpp
ab1b6c94039ae4b7d84361e48ec78e22c0c4f636  ./data_analytics/ext/xcl2/xcl2.hpp
8faace4fddb78a7a364d972bd13abb9a1ba7a8fc  ./data_compression/common/libs/xcl2/xcl2.hpp
508a1771aa3ed36c6b8bc0d2ae248e063ffa394c  ./utils/L2/tests/utils_sw/shared_host/xcl2/xcl2.hpp
7e6925513718737175c5413c58a9efde1bf86131  ./quantitative_finance/ext/xcl2/xcl2.hpp
3959e63c54da8831968f58d210f27f8bf69c9c4d  ./vision/ext/xcl2/xcl2.hpp

(I've reordered the output to cluster the similar sha1 together, they are from yesterday in the main branch).

Failed to compile 'host/concurrent_kernel_execution'

I am a beginner to Vitis. I'm trying the example in 'host/concurrent_kernel_execution'.

My command is as follows:

make all TARGET=hw_emu DEVICE=xilinx_u50_gen3x16_xdma_201920_3

Here is the full response:

g++ -o concurrent_kernel_execution /home/yzf/download/Vitis_Accel_Examples/common/includes/xcl2/xcl2.cpp src/host.cpp -I/opt/xilinx/xrt/include -I/home/yzf/FPGA/Vivado/2020.2/include -Wall -O0 -g -std=c++11 -I/home/yzf/download/Vitis_Accel_Examples/common/includes/xcl2 -fmessage-length=0 -L/opt/xilinx/xrt/lib -lOpenCL -lpthread  -lrt -lstdc++ 
mkdir -p ./_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3
v++ -t hw_emu --platform xilinx_u50_gen3x16_xdma_201920_3 --save-temps  -g -c -k madd --temp_dir ./_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3  -I'src' -o'_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/madd.xo' 'src/madd.cpp'
Option Map File Used: '/home/yzf/FPGA/Vitis/2020.2/data/vitis/vpp/optMap.xml'

****** v++ v2020.2 (64-bit)
  **** SW Build (by xbuild) on 2020-11-18-05:13:29
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
        Reports: /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/reports/madd
        Log files: /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/logs/madd
Running Dispatch Server on port:41803
INFO: [v++ 60-1548] Creating build summary session with primary output /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/madd.xo.compile_summary, at Wed Mar 24 16:51:54 2021
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Wed Mar 24 16:51:54 2021
Running Rule Check Server on port:44875
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/reports/madd/v++_compile_madd_guidance.html', at Wed Mar 24 16:51:55 2021
INFO: [v++ 60-895]   Target platform: /opt/xilinx/platforms/xilinx_u50_gen3x16_xdma_201920_3/xilinx_u50_gen3x16_xdma_201920_3.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/opt/xilinx/platforms/xilinx_u50_gen3x16_xdma_201920_3/hw/hw.xsa'
INFO: [v++ 74-74] Compiler Version string: 2020.2
INFO: [v++ 60-585] Compiling for hardware emulation target
INFO: [v++ 60-423]   Target device: xilinx_u50_gen3x16_xdma_201920_3
INFO: [v++ 60-242] Creating kernel: 'madd'
WARNING: /home/yzf/FPGA/Vitis/2020.2/tps/lnx64/jre9.0.4 does not exist.

===>The following messages were generated while  performing high-level synthesis for kernel: madd Log file: /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/madd/madd/vitis_hls.log :
INFO: [v++ 204-61] Pipelining loop 'madd_readA'.
INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'madd_readA'
INFO: [v++ 204-61] Pipelining loop 'madd_readB'.
INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'madd_readB'
INFO: [v++ 204-61] Pipelining loop 'madd_writeC'.
INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'madd_writeC'
INFO: [v++ 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [v++ 200-789] **** Estimated Fmax: 411.00 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/reports/madd/system_estimate_madd.xtxt
INFO: [v++ 60-586] Created _x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/madd.xo
INFO: [v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command. 
    vitis_analyzer /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/madd.xo.compile_summary 
INFO: [v++ 60-791] Total elapsed time: 0h 0m 42s
INFO: [v++ 60-1653] Closing dispatch client.
mkdir -p ./_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3
v++ -t hw_emu --platform xilinx_u50_gen3x16_xdma_201920_3 --save-temps  -g -c -k mscale --temp_dir ./_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3  -I'src' -o'_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/mscale.xo' 'src/mscale.cpp'
Option Map File Used: '/home/yzf/FPGA/Vitis/2020.2/data/vitis/vpp/optMap.xml'

****** v++ v2020.2 (64-bit)
  **** SW Build (by xbuild) on 2020-11-18-05:13:29
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
        Reports: /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/reports/mscale
        Log files: /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/logs/mscale
Running Dispatch Server on port:45013
INFO: [v++ 60-1548] Creating build summary session with primary output /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/mscale.xo.compile_summary, at Wed Mar 24 16:52:39 2021
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Wed Mar 24 16:52:39 2021
Running Rule Check Server on port:41989
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/reports/mscale/v++_compile_mscale_guidance.html', at Wed Mar 24 16:52:40 2021
INFO: [v++ 60-895]   Target platform: /opt/xilinx/platforms/xilinx_u50_gen3x16_xdma_201920_3/xilinx_u50_gen3x16_xdma_201920_3.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/opt/xilinx/platforms/xilinx_u50_gen3x16_xdma_201920_3/hw/hw.xsa'
INFO: [v++ 74-74] Compiler Version string: 2020.2
INFO: [v++ 60-585] Compiling for hardware emulation target
INFO: [v++ 60-423]   Target device: xilinx_u50_gen3x16_xdma_201920_3
INFO: [v++ 60-242] Creating kernel: 'mscale'
WARNING: /home/yzf/FPGA/Vitis/2020.2/tps/lnx64/jre9.0.4 does not exist.

===>The following messages were generated while  performing high-level synthesis for kernel: mscale Log file: /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/mscale/mscale/vitis_hls.log :
INFO: [v++ 204-61] Pipelining loop 'mscale'.
INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 5, loop 'mscale'
INFO: [v++ 204-61] Pipelining loop 'mscale_write'.
INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'mscale_write'
INFO: [v++ 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [v++ 200-789] **** Estimated Fmax: 411.00 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/reports/mscale/system_estimate_mscale.xtxt
INFO: [v++ 60-586] Created _x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/mscale.xo
INFO: [v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command. 
    vitis_analyzer /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/mscale.xo.compile_summary 
INFO: [v++ 60-791] Total elapsed time: 0h 0m 42s
INFO: [v++ 60-1653] Closing dispatch client.
mkdir -p ./_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3
v++ -t hw_emu --platform xilinx_u50_gen3x16_xdma_201920_3 --save-temps  -g -c -k mmult --temp_dir ./_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3  -I'src' -o'_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/mmult.xo' 'src/mmult.cpp'
Option Map File Used: '/home/yzf/FPGA/Vitis/2020.2/data/vitis/vpp/optMap.xml'

****** v++ v2020.2 (64-bit)
  **** SW Build (by xbuild) on 2020-11-18-05:13:29
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
        Reports: /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/reports/mmult
        Log files: /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/logs/mmult
Running Dispatch Server on port:42337
INFO: [v++ 60-1548] Creating build summary session with primary output /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/mmult.xo.compile_summary, at Wed Mar 24 16:53:23 2021
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Wed Mar 24 16:53:23 2021
Running Rule Check Server on port:40609
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/reports/mmult/v++_compile_mmult_guidance.html', at Wed Mar 24 16:53:25 2021
INFO: [v++ 60-895]   Target platform: /opt/xilinx/platforms/xilinx_u50_gen3x16_xdma_201920_3/xilinx_u50_gen3x16_xdma_201920_3.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/opt/xilinx/platforms/xilinx_u50_gen3x16_xdma_201920_3/hw/hw.xsa'
INFO: [v++ 74-74] Compiler Version string: 2020.2
INFO: [v++ 60-585] Compiling for hardware emulation target
INFO: [v++ 60-423]   Target device: xilinx_u50_gen3x16_xdma_201920_3
INFO: [v++ 60-242] Creating kernel: 'mmult'
WARNING: /home/yzf/FPGA/Vitis/2020.2/tps/lnx64/jre9.0.4 does not exist.

===>The following messages were generated while  performing high-level synthesis for kernel: mmult Log file: /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/mmult/mmult/vitis_hls.log :
INFO: [v++ 204-61] Pipelining loop 'mmult_readA'.
INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'mmult_readA'
INFO: [v++ 204-61] Pipelining loop 'mmult_readB'.
INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'mmult_readB'
INFO: [v++ 204-61] Pipelining loop 'mmult3'.
INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 5, loop 'mmult3'
INFO: [v++ 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [v++ 200-789] **** Estimated Fmax: 411.00 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/reports/mmult/system_estimate_mmult.xtxt
INFO: [v++ 60-586] Created _x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/mmult.xo
INFO: [v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command. 
    vitis_analyzer /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/mmult.xo.compile_summary 
INFO: [v++ 60-791] Total elapsed time: 0h 0m 43s
INFO: [v++ 60-1653] Closing dispatch client.
mkdir -p ./build_dir.hw_emu.xilinx_u50_gen3x16_xdma_201920_3
v++ -t hw_emu --platform xilinx_u50_gen3x16_xdma_201920_3 --save-temps  -g -l  --temp_dir ./build_dir.hw_emu.xilinx_u50_gen3x16_xdma_201920_3  -o'./build_dir.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/matrix_ops.link.xclbin' _x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/madd.xo _x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/mscale.xo _x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/mmult.xo
Option Map File Used: '/home/yzf/FPGA/Vitis/2020.2/data/vitis/vpp/optMap.xml'

****** v++ v2020.2 (64-bit)
  **** SW Build (by xbuild) on 2020-11-18-05:13:29
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
        Reports: /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/build_dir.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/reports/link
        Log files: /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/build_dir.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/logs/link
Running Dispatch Server on port:36585
INFO: [v++ 60-1548] Creating build summary session with primary output /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/build_dir.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/matrix_ops.link.xclbin.link_summary, at Wed Mar 24 16:54:09 2021
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Wed Mar 24 16:54:09 2021
Running Rule Check Server on port:37333
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/build_dir.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/reports/link/v++_link_matrix_ops.link_guidance.html', at Wed Mar 24 16:54:10 2021
INFO: [v++ 60-895]   Target platform: /opt/xilinx/platforms/xilinx_u50_gen3x16_xdma_201920_3/xilinx_u50_gen3x16_xdma_201920_3.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/opt/xilinx/platforms/xilinx_u50_gen3x16_xdma_201920_3/hw/hw.xsa'
INFO: [v++ 74-74] Compiler Version string: 2020.2
INFO: [v++ 60-629] Linking for hardware emulation target
INFO: [v++ 60-423]   Target device: xilinx_u50_gen3x16_xdma_201920_3
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [16:54:13] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/madd.xo --xo /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/mscale.xo --xo /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/mmult.xo -keep --xpfm /opt/xilinx/platforms/xilinx_u50_gen3x16_xdma_201920_3/xilinx_u50_gen3x16_xdma_201920_3.xpfm --target emu --output_dir /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/build_dir.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/link/int --temp_dir /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/build_dir.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/link/sys_link
INFO: [v++ 60-1454] Run Directory: /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/build_dir.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/link/run_link
INFO: [SYSTEM_LINK 60-1316] Initiating connection to rulecheck server, at Wed Mar 24 16:54:15 2021
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/madd.xo
ERROR: [KernelCheck 83-117] 'madd' kernel.xml indicates the existence of port S_AXI_CONTROL, which does not exist in component.xml
error: file /home/yzf/%E4%B8%8B%E8%BD%BD/Vitis_Accel_Examples/host/concurrent_kernel_execution/build_dir.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/link/sys_link/iprepo/temp/xo0/madd/kernel.xml
xsltRunStylesheet : run failed
ERROR: [SYSTEM_LINK 82-63] Error generating intermediate file /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/build_dir.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/link/sys_link/iprepo/temp/xo0/ip_repo/xilinx_com_hls_madd_1_0/madd.fcnmap.xml
ERROR: [SYSTEM_LINK 82-78] Unable to create function map for HLS kernel madd
ERROR: [SYSTEM_LINK 82-84] Unable to process .xo file: /home/yzf/download/Vitis_Accel_Examples/host/concurrent_kernel_execution/_x.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/madd.xo
ERROR: [SYSTEM_LINK 82-66] Error processing .xo files
ERROR: [SYSTEM_LINK 82-100] Error processing object files, exiting
INFO: [v++ 60-1442] [16:54:15] Run run_link: Step system_link: Failed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1580.469 ; gain = 0.000 ; free physical = 3930 ; free virtual = 14150
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
INFO: [v++ 60-1653] Closing dispatch client.
make: *** [Makefile:150：build_dir.hw_emu.xilinx_u50_gen3x16_xdma_201920_3/matrix_ops.xclbin] Error 1

I don't understand why there is such an error:

ERROR: [KernelCheck 83-117] 'madd' kernel.xml indicates the existence of port S_AXI_CONTROL, which does not exist in component.xml

I meet the same error when trying hw_emu in 'host/streaming_k2k_mm', while sw_emu in both example works fine. How should I deal with it?

Thanks a lot for any suggestion~

question about concurrent_kernel_execution

i use the demo of "/host/concurrent_kernel_execution" on the xilinx board -- Alveo U50.
when i make the software emulation , vitis shows the following error.

Found Platform
Platform Name: Xilinx
INFO: Reading ../matrix_ops.xclbin
Loading: '../matrix_ops.xclbin'
Trying to program device[0]: xilinx_u50_xdma_201920_1
ERROR: S_AXI_CONTROL remap entry is absent in xmlbin
ERROR: S_AXI_CONTROL remap entry is absent in xmlbin
ERROR: S_AXI_CONTROL remap entry is absent in xmlbin
XRT build version: 2.3.1301
Build hash: 192e706aea53163a04c574f9b3fe9ed76b6ca471
Build date: 2019-10-25 03:04:42
Git branch: 2019.2
PID: 55240
UID: 1007
[Tue Oct 20 14:44:46 2020]
HOST: B318
EXE: /home/ding/ghh/kernels_demo/demo/Emulation-SW/demo
[XRT] ERROR: Failed to load xclbin.
Failed to program device[0] with xclbin file!
Failed to program any device found, exit!

i don't understand where the errors they are , so i want to know how to deal with it.

thanks a lot!

folder path

Hello
is it possible please to put the common path into another repo please ? and so to use it in Vitis_Accel_Examples as a git submodule ?
So that every one will not have to clone all examples when they need to create their own project
it could be in Vitis_Accel_Common repo

@BhaskarVishnu

thank you

Running Hello world ( XILINX_VITIS variable not set)

Hi I have been trying to run hello world on the Xilinx alveo boards but I am constantly getting this error

utils.mk:30: *** XILINX_VITIS variable is not set, please set correctly and rerun. Stop.

This is the statement I am using to build the make file
make all TARGET=sw_emu DEVICE=xilinx_u280_xdma_201920_3 HOST_ARCH=x86

any suggestion ?

synth ERROR in U50 AAT design

Hi,

I use vitis, vivado 2020.2 for U50 accelerator, provided by xilinx.

INFO: [v++ 60-1454] Run Directory: /home/iiitb/Accelerated_Algorithmic_Trading/build/_x/link/run_link

INFO: [VPL 60-839] Read in kernel information from file '/home/iiitb/Accelerated_Algorithmic_Trading/build/_x/link/int/kernel_info.dat'.
INFO: [VPL 74-74] Compiler Version string: 2020.2
INFO: [VPL 60-423] Target device: xilinx_u50_gen3x16_xdma_201920_3
INFO: [VPL 60-1032] Extracting hardware platform to /home/iiitb/Accelerated_Algorithmic_Trading/build/_x/link/vivado/vpl/.local/hw_platform
WARNING: /tools/Vitis/Vitis/2020.2/tps/lnx64/jre9.0.4 does not exist.
[13:02:53] Run vpl: Step create_project: Started
Creating Vivado project.
[13:02:58] Run vpl: Step create_project: Completed
[13:02:58] Run vpl: Step create_bd: Started
[13:04:15] Run vpl: Step create_bd: RUNNING...
[13:05:06] Run vpl: Step create_bd: Completed
[13:05:06] Run vpl: Step update_bd: Started
[13:05:08] Run vpl: Step update_bd: Completed
[13:05:08] Run vpl: Step generate_target: Started
[13:06:23] Run vpl: Step generate_target: RUNNING...
[13:07:39] Run vpl: Step generate_target: RUNNING...
[13:08:54] Run vpl: Step generate_target: RUNNING...
[13:10:09] Run vpl: Step generate_target: RUNNING...
[13:10:35] Run vpl: Step generate_target: Completed
[13:10:35] Run vpl: Step config_hw_runs: Started
[13:10:41] Run vpl: Step config_hw_runs: Completed
[13:10:41] Run vpl: Step synth: Started
[13:11:43] Block-level synthesis in progress, 0 of 12 jobs complete, 4 jobs running.
[13:12:17] Block-level synthesis in progress, 0 of 12 jobs complete, 4 jobs running.
[13:12:48] Block-level synthesis in progress, 0 of 12 jobs complete, 4 jobs running.
[13:13:19] Block-level synthesis in progress, 0 of 12 jobs complete, 4 jobs running.
[13:13:49] Block-level synthesis in progress, 0 of 12 jobs complete, 4 jobs running.
[13:14:20] Block-level synthesis in progress, 0 of 12 jobs complete, 4 jobs running.
[13:14:51] Block-level synthesis in progress, 0 of 12 jobs complete, 4 jobs running.
[13:15:22] Block-level synthesis in progress, 0 of 12 jobs complete, 4 jobs running.
[13:15:55] Block-level synthesis in progress, 0 of 12 jobs complete, 4 jobs running.
[13:16:28] Block-level synthesis in progress, 0 of 12 jobs complete, 4 jobs running.
[13:20:07] Block-level synthesis in progress, 0 of 12 jobs complete, 4 jobs running.
[13:20:09] Block-level synthesis in progress, 0 of 12 jobs complete, 4 jobs running.
[13:20:09] Run vpl: FINISHED. Run Status: synth ERROR
WARNING: [VPL 60-732] Link warning: No monitor points found for BD automation.
ERROR: [VPL 60-1328] Vpl run 'vpl' failed
WARNING: [VPL 60-1142] Unable to read data from '/home/iiitb/Accelerated_Algorithmic_Trading/build/_x/link/vivado/vpl/output/generated_reports.log', generated reports will not be copied.
ERROR: [VPL 60-806] Failed to finish platform linker
INFO: [v++ 60-1442] [13:20:12] Run run_link: Step vpl: Failed
Time (s): cpu = 00:07:52 ; elapsed = 00:17:53 . Memory (MB): peak = 1577.230 ; gain = 0.000 ; free physical = 149 ; free virtual = 2751
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
INFO: [v++ 60-1653] Closing dispatch client.
make: *** [Makefile:206: aat.xclbin] Error 1

Can you please tell me how to solve this problem?

I am attaching the log file.

Thanks in Advance

Problem about Use Vitis IDE to build Kmeans demo

Hello,

How to reproduce:
I took the code from the latest branch and compiled it with a 2020.2 Vitis IDE.

The problem was observed xilinx_u200_xdma_201830_2 platform, and with XRT 2020.2.
The Host system was Ubuntu 16.04. The Vitis IDE's version is v2020.2.0(64bit).

Error:
I create a new application project that uses the Kmeans sample code in the Vitis_Accel_Examples. An error occurred when I tried to compile it using Emulation_sw. I don't do anything to change the code.

The problems show:

Errors(2 items)
make:***[package]Error1`
make:***no rule to make target 'krnl_kmeans.cfg', needed by 'krnl_kmeans.xclbin'. Stop`

How could I fix it and compile it successfully?

Thank,
Hundan

Perl not found with "hello_world" example with ZCU102 device

Has anyone gone through the "hello_world" example with ZCU102 device? I am running ubuntu 16.04.6 with Vitis, Vivado, PetaLinux 2020.1 all installed under /tools/Xilinx/

After make "all" with: make all TARGET=sw_emu DEVICE=xilinx_zcu102_base_202010_1 HOST_ARCH=aarch64 SYSROOT=~/xilinx-zynqmp-common-v2020.1/ir/sysroots/aarch64-xilinx-linux

I try to run make "check: with: make check TARGET=sw_emu DEVICE=xilinx_zcu102_base_202010_1 HOST_ARCH=aarch64 SYSROOT=~/xilinx-zynqmp-common-v2020.1/ir/sysroots/aarch64-xilinx-linux

but it outputs:
/bin/sh: /home/ywongai/Vitis_Accel_Examples/common/utility/run_emulation.pl: /tools/xgs/perl/5.8.5/bin/perl: bad interpreter: No such file or directory

Full output of make check:
ywongai@linuxhost:~/Vitis_Accel_Examples/hello_world$ make check TARGET=sw_emu DEVICE=xilinx_zcu102_base_202010_1 HOST_ARCH=aarch64 SYSROOT=/home/ywongai/xilinx-zynqmp-common-v2020.1/ir/sysroots/aarch64-xilinx-linux
/tools/Xilinx/Vitis/2020.1/gnu/aarch64/lin/aarch64-linux/bin/aarch64-linux-gnu-g++ -I..//common/includes/xcl2 -I/home/ywongai/xilinx-zynqmp-common-v2020.1/ir/sysroots/aarch64-xilinx-linux/usr/include/xrt -I/tools/Xilinx/Vivado/2020.1/include -Wall -O0 -g -std=c++11 -fmessage-length=0 ..//common/includes/xcl2/xcl2.cpp src/host.cpp -o 'host' -L/home/ywongai/xilinx-zynqmp-common-v2020.1/ir/sysroots/aarch64-xilinx-linux/usr/lib -lOpenCL -lpthread -lrt -lstdc++ --sysroot=/home/ywongai/xilinx-zynqmp-common-v2020.1/ir/sysroots/aarch64-xilinx-linux
rm -rf run_app.sh
v++ -t sw_emu --platform xilinx_zcu102_base_202010_1 -p ./build_dir.sw_emu.xilinx_zcu102_base_202010_1/vadd.xclbin --package.out_dir package.sw_emu --package.rootfs /home/ywongai/xilinx-zynqmp-common-v2020.1/rootfs.ext4 --package.sd_file /home/ywongai/xilinx-zynqmp-common-v2020.1/Image --package.sd_file xrt.ini --package.sd_file run_app.sh --package.sd_file host -o vadd.xclbin
Option Map File Used: '/tools/Xilinx/Vitis/2020.1/data/vitis/vpp/optMap.xml'

INFO: [v++ 60-1306] Additional information associated with this v++ package can be found at:
Reports: /home/ywongai/Vitis_Accel_Examples/hello_world/_x/reports/package
Log files: /home/ywongai/Vitis_Accel_Examples/hello_world/_x/logs/package
INFO: [v++ 60-1657] Initializing dispatch client.
Running Dispatch Server on port:34295
INFO: [v++ 60-1548] Creating build summary session with primary output /home/ywongai/Vitis_Accel_Examples/hello_world/vadd.xclbin.package_summary, at Tue Aug 18 12:34:56 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Tue Aug 18 12:34:56 2020
Running Rule Check Server on port:34423
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/ywongai/Vitis_Accel_Examples/hello_world/_x/reports/package/v++_package_vadd_guidance.html', at Tue Aug 18 12:34:57 2020
INFO: [v++ 60-895] Target platform: /tools/Xilinx/Vitis/2020.1/platforms/xilinx_zcu102_base_202010_1/xilinx_zcu102_base_202010_1.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/tools/Xilinx/Vitis/2020.1/platforms/xilinx_zcu102_base_202010_1/hw/xilinx_zcu102_base_202010_1.xsa'
INFO: [v++ 60-2256] Packaging for software emulation
WARNING: [v++ 82-1077] Kernel image is not specified for linux domain
WARNING: [v++ 82-1097] Skipping boot image generation, since FSBL is directly loaded onto emulator
INFO: [v++ 82-1017] Deleting existing qemu_args.txt
INFO: [v++ 82-1016] Deleting existing pmc_args.txt
INFO: [v++ 82-1014] Deleting existing launch_hw_emulator.sh
INFO: [v++ 82-1022] Generating /home/ywongai/Vitis_Accel_Examples/hello_world/package.sw_emu/launch_sw_emu.sh
INFO: [v++ 82-1018] Deleting existing sd_card directory
INFO: [v++ 82-1011] Creating sd_card directory
INFO: [v++ 82-1075] Deleting the existing directory /home/ywongai/Vitis_Accel_Examples/hello_world/package.sw_emu/sd_card//data/emulation/unified
INFO: [v++ 82-1083] Deleting existing sd_card.img
FATSIZE:1124
fat_start:63
fat_end:2096639
fat_sector:2096577
ext4_start:0
ext4_sector:4142856
EXT4SIZE:2048
TOTALSIZE:3172
dummy_ext4_sector:51448
sd_card_fat_start:2048
sd_card_ext4_start:2195456
dummy_ext4_start:6338312
2096577+0 records in
2096577+0 records out
1073447424 bytes (1.1 GB, 1.0 GiB) copied, 6.1871 s, 173 MB/s
4142856+0 records in
4142856+0 records out
2121142272 bytes (2.1 GB, 2.0 GiB) copied, 11.088 s, 191 MB/s
51448+0 records in
51448+0 records out
26341376 bytes (26 MB, 25 MiB) copied, 0.129789 s, 203 MB/s
INFO: [v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command.
vitis_analyzer /home/ywongai/Vitis_Accel_Examples/hello_world/vadd.xclbin.package_summary
INFO: [v++ 60-791] Total elapsed time: 0h 0m 33s
INFO: [v++ 60-1653] Closing dispatch client.
/home/ywongai/Vitis_Accel_Examples/common/utility/run_emulation.pl "./package.sw_emu/launch_sw_emu.sh | tee run_app.log" "./run_app.sh sw_emu" "TEST PASSED" "7"
/bin/sh: /home/ywongai/Vitis_Accel_Examples/common/utility/run_emulation.pl: /tools/xgs/perl/5.8.5/bin/perl: bad interpreter: No such file or directory
make: *** [Makefile:132: check] Error 126

errors on "kmeans example"

 make all TARGET=sw_emu PLATFORM=xilinx_u200_xdma_201830_2 HOST_ARCH=x86
g++ -o kmeans /home/enai/Desktop/project/enai0/Vitis_Accel_Examples/common/includes/xcl2/xcl2.cpp /home/enai/Desktop/project/enai0/Vitis_Accel_Examples/common/includes/cmdparser/cmdlineparser.cpp /home/enai/Desktop/project/enai0/Vitis_Accel_Examples/common/includes/logger/logger.cpp src/host.cpp src/fpga_kmeans.cpp src/kmeans_clustering_cmodel.c -D __USE_OPENCL__ -DNUM_CU=2 -I/opt/xilinx/xrt/include -I/tools/Xilinx/Vivado/2020.1/include -Wall -O0 -g -std=c++1y -I/home/enai/Desktop/project/enai0/Vitis_Accel_Examples/common/includes/xcl2 -I/home/enai/Desktop/project/enai0/Vitis_Accel_Examples/common/includes/cmdparser -I/home/enai/Desktop/project/enai0/Vitis_Accel_Examples/common/includes/logger -fmessage-length=0 -L/opt/xilinx/xrt/lib -lOpenCL -pthread -lrt -lstdc++ 
In file included from /home/enai/Desktop/project/enai0/Vitis_Accel_Examples/common/includes/xcl2/xcl2.cpp:17:0:
/home/enai/Desktop/project/enai0/Vitis_Accel_Examples/common/includes/xcl2/xcl2.hpp:33:10: fatal error: CL/cl2.hpp: No such file or directory
 #include <CL/cl2.hpp>
          ^~~~~~~~~~~~
compilation terminated.
In file included from src/fpga_kmeans.h:28:0,
                 from src/host.cpp:56:
/home/enai/Desktop/project/enai0/Vitis_Accel_Examples/common/includes/xcl2/xcl2.hpp:33:10: fatal error: CL/cl2.hpp: No such file or directory
 #include <CL/cl2.hpp>
          ^~~~~~~~~~~~
compilation terminated.
In file included from src/fpga_kmeans.h:28:0,
                 from src/fpga_kmeans.cpp:17:
/home/enai/Desktop/project/enai0/Vitis_Accel_Examples/common/includes/xcl2/xcl2.hpp:33:10: fatal error: CL/cl2.hpp: No such file or directory
 #include <CL/cl2.hpp>
          ^~~~~~~~~~~~
compilation terminated.
Makefile:158: recipe for target 'kmeans' failed
make: *** [kmeans] Error 1

Error when creating example project of RTL Kernel Wizard IP

I am following the rtl_streaming_k2k_mm example to package RTL kernels into XO files, and make them callable from host. The TCL script for generating XO files (i.e.src/gen_xo_myadder1.tcl) works fine with the default kernel type RTL, but failed with the type Block Design. The error message is shown as below.

ERROR: [xilinx.com:ip:rtl_kernel_wizard:1.0-100] Failed to execute xsct to create and build software: "child process exited abnormally", please check rtl_streaming_k2k_mm/myadder2_ex/myadder2_ex.sdk/xsct.log for more details.
ERROR: [open_example_project] Open Example Project failed: Error encountered while sourcing custom IP example design script.
ERROR: [Common 17-39] 'send_msg_id' failed due to earlier errors.

Error message from the log file:

Starting vitis. This could take few seconds...WARNING: Using incubator modules: jdk.incubator.httpclient
done
INFO: [Hsi 55-2053] elapsed time for repository (/work/shared/common/Xilinx/Vitis/2019.2/data/embeddedsw) loading 2 seconds
Opening the hardware design, this may take few seconds.
/work/shared/common/Xilinx/Vitis/2019.2/gnu/microblaze/lin
error deleting "./src/arm/common": file already exists
ERROR: [Hsi 55-1545] Problem running tcl command ::sw_standalone_v7_1::generate : error deleting "./src/arm/common": file already exists
    while executing

From the document, the RTL Kernel Wizard will generate a MicroBlaze IP for the example project with kernel type "Block design". What is the cause this issue? Is there any tutorial on how to create RTL kernel for Vitis using custom BD design?

Error in creating xcbin

https://forums.xilinx.com/t5/Vitis-Acceleration-SDAccel-SDSoC/Failed-to-create-xcbin-for-gemm-operation/td-p/1151871

System crashed when running P2P_bandwidth on U250

Hi, I used command make all TARGET=hw PLATFORM=xilinx_u250_gen3x16_xdma_3_1_202020_1 to obtain the bandwidth.xclbin and p2p_bandwidth. However, the system crashed when running ./p2p_bandwidth -x ./build_dir.hw.xilinx_u250_gen3x16_xdma_3_1_202020_1/bandwidth.xclbin -f ./data/sample.txt.

Other info may be useful: I can successfully run the p2p_simple example, the p2p feature is enabled. When running p2p_bandwidth, the xclbin file was successfully programmed. The system crashed after output Start P2P Write of various buffer sizes from device buffers to SSD. Vitis and XRT version: 2020.2. XRT build version: 2.8.743. OS: ubuntu 18.04.

Looking forward to your reply. Thanks.

PLRAM Example shows error

The plram example shows error as:
[XRT] ERROR: context is nullptr
[XRT] ERROR: context is nullptr

mullt.ini has the connectivity but still its not able to differentiate banks
The flag XCL_MEM_PLRAM_BANK3 is not applicable to plram.
What flay can be used used for PLRAM

TEST helloworld demo ERROR

Hi， when i test helloworld ，There is an error as follow
[ding@B318 hello_world]$ make all TARGET=sw_emu DEVICE=xilinx_u50_xdma_201920_1
mkdir -p ./build_dir.sw_emu.xilinx_u50_xdma_201920_1
v++ -l -t sw_emu --platform xilinx_u50_xdma_201920_1 --save-temps -g --temp_dir ./build_dir.sw_emu.xilinx_u50_xdma_201920_1 -o'./build_dir.sw_emu.xilinx_u50_xdma_201920_1/vadd.link.xclbin' _x.sw_emu.xilinx_u50_xdma_201920_1/vadd.xo
Option Map File Used: '/tools/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'

INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
Reports: /hdd/F_C_ding/Vitis_Accel_Examples/hello_world/build_dir.sw_emu.xilinx_u50_xdma_201920_1/reports/link
Log files: /hdd/F_C_ding/Vitis_Accel_Examples/hello_world/build_dir.sw_emu.xilinx_u50_xdma_201920_1/logs/link
Running Dispatch Server on port:44082
INFO: [v++ 60-1548] Creating build summary session with primary output /hdd/F_C_ding/Vitis_Accel_Examples/hello_world/build_dir.sw_emu.xilinx_u50_xdma_201920_1/vadd.link.xclbin.link_summary, at Wed Jan 20 14:54:38 2021
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Wed Jan 20 14:54:38 2021
Running Rule Check Server on port:40035
INFO: [v++ 60-1315] Creating rulecheck session with output '/hdd/F_C_ding/Vitis_Accel_Examples/hello_world/build_dir.sw_emu.xilinx_u50_xdma_201920_1/reports/link/v++_link_vadd.link_guidance.html', at Wed Jan 20 14:54:39 2021
INFO: [v++ 60-895] Target platform: /opt/xilinx/platforms/xilinx_u50_xdma_201920_1/xilinx_u50_xdma_201920_1.xpfm
INFO: [v++ 60-1578] This platform contains Device Support Archive '/opt/xilinx/platforms/xilinx_u50_xdma_201920_1/hw/xilinx_u50_xdma_201920_1.dsa'
INFO: [v++ 60-629] Linking for software emulation target
INFO: [v++ 60-423] Target device: xilinx_u50_xdma_201920_1
INFO: [v++ 60-645] kernel flags are '-g -I /hdd/F_C_ding/Vitis_Accel_Examples/hello_world/src -g'
INFO: [v++ 60-586] Created ./build_dir.sw_emu.xilinx_u50_xdma_201920_1/vadd.link.xclbin
INFO: [v++ 60-1307] Run completed. Additional information can be found in:
Guidance: /hdd/F_C_ding/Vitis_Accel_Examples/hello_world/build_dir.sw_emu.xilinx_u50_xdma_201920_1/reports/link/v++_link_vadd.link_guidance.html
Steps Log File: /hdd/F_C_ding/Vitis_Accel_Examples/hello_world/build_dir.sw_emu.xilinx_u50_xdma_201920_1/logs/link/link.steps.log

INFO: [v++ 60-791] Total elapsed time: 0h 0m 9s
v++ -p ./build_dir.sw_emu.xilinx_u50_xdma_201920_1/vadd.link.xclbin -t sw_emu --platform xilinx_u50_xdma_201920_1 --package.out_dir ./package.sw_emu -o ./build_dir.sw_emu.xilinx_u50_xdma_201920_1/vadd.xclbin
ERROR: [v++ 60-1520] ***Exception: unrecognised option '-p'
usage: v++ [options]

Because it's the first time，hope some advices ,thankyou.

Error when running 'Hello_world' on U50

Hi, after compiling for Alveo U50 Accelerator Card by coding make all DEVICE=xilinx_u50_gen3x16_xdma_201920_3 TARGET=hw command the vadd.xclbin was generated in fold build_dir.hw.xilinx_u50_gen3x16_xdma_201920_3. When I code ./hello_world '/home/username/Vitis_Accel_Examples-master/hello_world/build_dir.hw.xilinx_u50_gen3x16_xdma_201920_3/vadd.xclbin' some error occured and there was no output. Here follows the error info:

XRT build version: 2.11.634
Build hash: 5ad5998d67080f00bca5bf15b3838cf35e0a7b26
Build date: 2021-06-08 22:08:45
Git branch: 2021.1
PID: 1868037
UID: 1008
[Wed Dec  1 01:16:16 2021 GMT]
HOST: server-94
EXE: /home/username/Vitis_Accel_Examples-master/hello_world/hello_world
[XRT] WARNING: "profile" configuration in xrt.ini will be deprecated in the next release.  Please use "opencl_summary=true" to enable OpenCL profiling and "opencl_device_counter=true" for device counter data in OpenCL profile summary.
Found Platform
Platform Name: Xilinx
INFO: Reading /home/username/Vitis_Accel_Examples-master/hello_world/build_dir.hw.xilinx_u50_gen3x16_xdma_201920_3/vadd.xclbin
Loading: '/home/username/Vitis_Accel_Examples-master/hello_world/build_dir.hw.xilinx_u50_gen3x16_xdma_201920_3/vadd.xclbin'
Trying to program device[0]: xilinx_u50_gen3x16_xdma_201920_3
Device[0]: program successful!
terminate called recursively
terminate called after throwing an instance of '__gnu_cxx::recursive_init_error'
Aborted (core dumped)

Looking forward to your reply.

Build Vitis_Accel_Examples/sys_opt/multiple_process/ project fail

For this project: Vitis_Accel_Examples/sys_opt/multiple_process/
When bulid the project from command line: the three xo files can be generated, but during the link stage, error report:

INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /home/vitis_workspace_new/Vitis_Accel_Examples/sys_opt/multiple_process/_x.hw.xilinx_u200_xdma_201830_2/krnl_vadd.xo
ERROR: [KernelCheck 83-117] '' kernel.xml indicates the existence of port , which does not exist
ERROR: [SYSTEM_LINK 82-63] Error generating intermediate file /home/vitis_workspace_new/Vitis_Accel_Examples/sys_opt/multiple_process/build_dir.hw.xilinx_u200_xdma_201830_2/link/sys_link/iprepo/temp/xo0/ip_repo/xilinx_com_hls_krnl_vadd_1_0/krnl_vadd.fcnmap.xml
ERROR: [SYSTEM_LINK 82-78] Unable to create function map for HLS kernel krnl_vadd
ERROR: [SYSTEM_LINK 82-84] Unable to process .xo file: /home/vitis_workspace_new/Vitis_Accel_Examples/sys_opt/multiple_process/_x.hw.xilinx_u200_xdma_201830_2/krnl_vadd.xo
ERROR: [SYSTEM_LINK 82-66] Error processing .xo files
ERROR: [SYSTEM_LINK 82-100] Error processing object files, exiting
INFO: [v++ 60-1442] [09:46:33] Run run_link: Step system_link: Failed
Time (s): cpu = 00:00:00.84 ; elapsed = 00:00:00.92 . Memory (MB): peak = 674.820 ; gain = 0.000 ; free physical = 50142 ; free virtual = 61457
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking

Warning when build the kernel image

When I run the tcl script to build the rtl image of this project:
https://github.com/Xilinx/Vitis_Accel_Examples/blob/2020.1/rtl_kernels/rtl_vadd_hw_debug/scripts/package_kernel.tcl

These are such warning message :
WARNING: [IP_Flow 19-3158] Bus Interface 'm_axi_gmem': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 's_axi_control': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3157] Bus Interface 'ap_rst_n': Bus parameter POLARITY is ACTIVE_LOW but port 'ap_rst_n' is not *resetn - please double check the POLARITY setting. WARNING: [IP_Flow 19-5661] Bus Interface 'ap_clk' does not have any bus interfaces associated with it.
Do these warnings matter and how to remove them?

Deadlock within rtl_vadd_2clks example, when setting DATA_SIZE to 1025 in host.cpp

Hello,

How to reproduce:
I took the code from the 2019.2 branch and compiled with a 2019.2 Vitis.

The problem was observed xilinx_u200_xdma_201830_2 platform, and with XRT 2020.1.
When changing in the host the DATA_SIZE to 1025 and running several times the example, the process will eventually get locked (most often, two runs are enough; the first run always succeed).

Here is the xbutil query trace:

INFO: Found total 1 card(s), 1 are usable
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
System Configuration
OS name:	Linux
Release:	3.10.0-1127.13.1.el7.x86_64
Version:	#1 SMP Fri Jun 12 14:34:17 EDT 2020
Machine:	x86_64
Model:		PowerEdge T630
CPU cores:	24
Memory:		257693 MB
Glibc:		2.27
Distribution:	Ubuntu 18.04.5 LTS
Now:		Wed Aug 26 15:36:22 2020
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
XRT Information
Version:	2.6.655
Git Hash:	2d6bfe4ce91051d4e5b499d38fc493586dd4859a
Git Branch:	2020.1
Build Date:	2020-05-22 12:05:03
XOCL:		2.6.655,2d6bfe4ce91051d4e5b499d38fc493586dd4859a
XCLMGMT:	2.6.655,2d6bfe4ce91051d4e5b499d38fc493586dd4859a

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Shell                           FPGA                            IDCode
xilinx_u200_xdma_201830_2       xcu200-fsgd2104-2-e             0x14b37093
Vendor          Device          SubDevice       SubVendor       SerNum          
0x10ee          0x5001          0x000e          0x10ee          2129048AJ017    
DDR size        DDR count       Clock0          Clock1          Clock2          
64 GB           4               150             250             0               
PCIe            DMA chan(bidir) MIG Calibrated  P2P Enabled     OEM ID          
GEN 3x16        2               true            false           0xc6f50640(N/A) 
DNA

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Temperature(C)
PCB TOP FRONT   PCB TOP REAR    PCB BTM FRONT   VCCINT TEMP     
41              35              40              N/A             
FPGA TEMP       TCRIT Temp      FAN Presence    FAN Speed(RPM)  
42              40              A               1110            
QSFP 0          QSFP 1          QSFP 2          QSFP 3          
N/A             N/A             N/A             N/A             
HBM TEMP        
N/A             
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Electrical(mV|mA)
12V PEX         12V AUX         12V PEX Current 12V AUX Current 
12265           12257           1124            969             
3V3 PEX         3V3 AUX         DDR VPP BOTTOM  DDR VPP TOP     
3363            3300            2500            2500            
SYS 5V5         1V2 TOP         1V8 TOP         0V85            
5471            1206            1835            857             
MGT 0V9         12V SW          MGT VTT         1V2 BTM         
909             12190           1202            1202            
VCCINT VOL      VCCINT CURR     VCCINT IO VOL   VCC3V3 VOL      
851             12240           N/A             N/A             
3V3 PEX CURR    VCCINT IO CURR  HBM1V2 VOL      VPP2V5 VOL      
N/A             N/A             N/A             N/A             
VCC1V2 CURR     V12 I CURR      V12 AUX0 CURR   V12 AUX1 CURR   
N/A             N/A             N/A             N/A             
12V AUX1 VOL    VCCAUX VOL      VCCAUX PMC VOL  VCCRAM VOL      
N/A             N/A             N/A             N/A             
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Card Power(W)
25
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Firewall Last Error Status
Level 0 : 0x0(GOOD)

ECC Error Status
Tag     Errors      CE Count  UE Count  CE FFA              UE FFA              
bank1   (None)      0         0         0x0                 0x0                 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Memory Status
     Tag         Type        Temp(C)  Size    Mem Usage       BO count
[ 0] bank0       **UNUSED**  33       16 GB   0 Byte          0       
[ 1] bank1       MEM_DDR4    36       16 GB   24576 Byte      3       
[ 2] bank2       **UNUSED**  39       16 GB   0 Byte          0       
[ 3] bank3       **UNUSED**  36       16 GB   0 Byte          0       
[ 4] PLRAM[0]    **UNUSED**  N/A      128 KB  0 Byte          0       
[ 5] PLRAM[1]    **UNUSED**  N/A      128 KB  0 Byte          0       
[ 6] PLRAM[2]    **UNUSED**  N/A      128 KB  0 Byte          0       
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
DMA Transfer Metrics
Chan[0].h2c:  17175 KB
Chan[0].c2h:  272 KB
Chan[1].h2c:  8200 Byte
Chan[1].c2h:  0 Byte
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Streams
     Tag         Flow ID  Route ID Status   Total (B/#)     Pending (B/#)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Xclbin UUID
7f4e0c0e-8c43-4b75-9c57-a4a495b6d6fb
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Compute Unit Status
CU[ 0]: krnl_vadd_rtl:krnl_vadd_rtl_1   @0x1800000         (START)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
INFO: xbutil query succeeded.
nbondoux@46a6ad77bae8:/projects/nbondoux/erbium_master/xilinx_work$ xbutil reset
All existing processes will be killed.
Are you sure you wish to proceed? [y/n]: y
nbondoux@46a6ad77bae8:/projects/nbondoux/erbium_master/xilinx_work$ xbutil query
INFO: Found total 1 card(s), 1 are usable
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
System Configuration
OS name:	Linux
Release:	3.10.0-1127.13.1.el7.x86_64
Version:	#1 SMP Fri Jun 12 14:34:17 EDT 2020
Machine:	x86_64
Model:		PowerEdge T630
CPU cores:	24
Memory:		257693 MB
Glibc:		2.27
Distribution:	Ubuntu 18.04.5 LTS
Now:		Wed Aug 26 15:37:27 2020
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
XRT Information
Version:	2.6.655
Git Hash:	2d6bfe4ce91051d4e5b499d38fc493586dd4859a
Git Branch:	2020.1
Build Date:	2020-05-22 12:05:03
XOCL:		2.6.655,2d6bfe4ce91051d4e5b499d38fc493586dd4859a
XCLMGMT:	2.6.655,2d6bfe4ce91051d4e5b499d38fc493586dd4859a

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Shell                           FPGA                            IDCode
xilinx_u200_xdma_201830_2       xcu200-fsgd2104-2-e             0x14b37093
Vendor          Device          SubDevice       SubVendor       SerNum          
0x10ee          0x5001          0x000e          0x10ee          2129048AJ017    
DDR size        DDR count       Clock0          Clock1          Clock2          
64 GB           4               150             250             0               
PCIe            DMA chan(bidir) MIG Calibrated  P2P Enabled     OEM ID          
GEN 3x16        2               true            false           0x200f0640(N/A) 
DNA

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Temperature(C)
PCB TOP FRONT   PCB TOP REAR    PCB BTM FRONT   VCCINT TEMP     
41              35              41              N/A             
FPGA TEMP       TCRIT Temp      FAN Presence    FAN Speed(RPM)  
42              40              A               1110            
QSFP 0          QSFP 1          QSFP 2          QSFP 3          
N/A             N/A             N/A             N/A             
HBM TEMP        
N/A             
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Electrical(mV|mA)
12V PEX         12V AUX         12V PEX Current 12V AUX Current 
12242           12286           1152            961             
3V3 PEX         3V3 AUX         DDR VPP BOTTOM  DDR VPP TOP     
3366            3303            2500            2500            
SYS 5V5         1V2 TOP         1V8 TOP         0V85            
5496            1203            1842            855             
MGT 0V9         12V SW          MGT VTT         1V2 BTM         
908             12201           1203            1203            
VCCINT VOL      VCCINT CURR     VCCINT IO VOL   VCC3V3 VOL      
851             12306           N/A             N/A             
3V3 PEX CURR    VCCINT IO CURR  HBM1V2 VOL      VPP2V5 VOL      
N/A             N/A             N/A             N/A             
VCC1V2 CURR     V12 I CURR      V12 AUX0 CURR   V12 AUX1 CURR   
N/A             N/A             N/A             N/A             
12V AUX1 VOL    VCCAUX VOL      VCCAUX PMC VOL  VCCRAM VOL      
N/A             N/A             N/A             N/A             
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Card Power(W)
25
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Firewall Last Error Status
Level 0 : 0x0(GOOD)

ECC Error Status
Tag     Errors      CE Count  UE Count  CE FFA              UE FFA              
bank1   (None)      0         0         0x0                 0x0                 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Memory Status
     Tag         Type        Temp(C)  Size    Mem Usage       BO count
[ 0] bank0       **UNUSED**  33       16 GB   0 Byte          0       
[ 1] bank1       MEM_DDR4    36       16 GB   24576 Byte      3       
[ 2] bank2       **UNUSED**  39       16 GB   0 Byte          0       
[ 3] bank3       **UNUSED**  36       16 GB   0 Byte          0       
[ 4] PLRAM[0]    **UNUSED**  N/A      128 KB  0 Byte          0       
[ 5] PLRAM[1]    **UNUSED**  N/A      128 KB  0 Byte          0       
[ 6] PLRAM[2]    **UNUSED**  N/A      128 KB  0 Byte          0       
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
DMA Transfer Metrics
Chan[0].h2c:  8200 Byte
Chan[0].c2h:  4100 Byte
Chan[1].h2c:  8200 Byte
Chan[1].c2h:  0 Byte
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Streams
     Tag         Flow ID  Route ID Status   Total (B/#)     Pending (B/#)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Xclbin UUID
7f4e0c0e-8c43-4b75-9c57-a4a495b6d6fb
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Compute Unit Status
CU[ 0]: krnl_vadd_rtl:krnl_vadd_rtl_1   @0x1800000         (START)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
INFO: xbutil query succeeded.

Thanks,
Nicolas

Question about the CU Utilization

Hi, I have a question about the CU utilization of the array partition (cpp_kernels) example. If the overall Avg latencies of normal kernel and partition kernel are 9.522 us and 3.540 us respectively, why the Wall-Clock Time of hw execution results are 396685 ns and 256367 ns respectively? In other words, how could I achieve a higher CU utilization?

Segmentation fault during build

Hi, I was building the rtl_vadd example code with 2019.2 branch and there is segmentation fault error.

The detail command and the log output is the following:

make all TARGET=hw DEVICE=/opt/xilinx/platforms/xilinx_u280_xdma_201920_3/xilinx_u280_xdma_201920_3.xpfm

g++ -I../..//common/includes/xcl2 -I/opt/xilinx/xrt/include -I/opt/Xilinx/Vivado/2019.2/include -Wall -O0 -g -std=c++11 -fmessage-length=0 ../..//common/includes/xcl2/xcl2.cpp src/host.cpp -o 'host' -L/opt/xilinx/xrt/lib -lOpenCL -lpthread -lrt -lstdc++
mkdir -p ./_x.hw.xilinx_u280_xdma_201920_3
/opt/Xilinx/Vivado/2019.2/bin/vivado -mode batch -source scripts/gen_xo.tcl -tclargs ./_x.hw.xilinx_u280_xdma_201920_3/vadd.xo vadd hw /opt/xilinx/platforms/xilinx_u280_xdma_201920_3/xilinx_u280_xdma_201920_3.xpfm xilinx_u280_xdma_201920_3

source scripts/gen_xo.tcl
INFO: [IP_Flow 19-5169] Module 'krnl_vadd_rtl' uses SystemVerilog sources with a Verilog top file. These SystemVerilog files will not be analysed by the packager.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_gmem' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_control' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'interrupt' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'ap_rst_n': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'interrupt': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'ap_rst_n'.
WARNING: [IP_Flow 19-3158] Bus Interface 'm_axi_gmem': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 's_axi_control': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3157] Bus Interface 'ap_rst_n': Bus parameter POLARITY is ACTIVE_LOW but port 'ap_rst_n' is not *resetn - please double check the POLARITY setting.
WARNING: [IP_Flow 19-3153] Bus Interface 'ap_clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [IP_Flow 19-795] Syncing license key meta-data
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/packaged_kernel_vadd_hw_xilinx_u280_xdma_201920_3/src/krnl_vadd_rtl_control_s_axi.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/packaged_kernel_vadd_hw_xilinx_u280_xdma_201920_3/src/krnl_vadd_rtl_adder.sv:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/packaged_kernel_vadd_hw_xilinx_u280_xdma_201920_3/src/krnl_vadd_rtl_axi_read_master.sv:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/packaged_kernel_vadd_hw_xilinx_u280_xdma_201920_3/src/krnl_vadd_rtl_axi_write_master.sv:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/packaged_kernel_vadd_hw_xilinx_u280_xdma_201920_3/src/krnl_vadd_rtl_counter.sv:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/packaged_kernel_vadd_hw_xilinx_u280_xdma_201920_3/src/krnl_vadd_rtl_int.sv:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/packaged_kernel_vadd_hw_xilinx_u280_xdma_201920_3/src/krnl_vadd_rtl.v:]
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axi_gmem'.
WARNING: [IP_Flow 19-3157] Bus Interface 'ap_rst_n': Bus parameter POLARITY is ACTIVE_LOW but port 'ap_rst_n' is not *resetn - please double check the POLARITY setting.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed.

WARNING: [Vivado 12-4404] The CPU emulation flow in v++ is only supported when using a packaged XO file that contains C-model files, none were found.
WARNING: [Vivado 12-7038] The bus parameter 'ap_clk.FREQ_HZ' has been detected in the kernel IP 'krnl_vadd_rtl'. This may cause validation errors in v++ if a target platform has a different default kernel clock frequency. If validation errors do occur in v++, please edit and re-generate the kernel IP 'krnl_vadd_rtl' to remove the bus parameter 'ap_clk.FREQ_HZ'
INFO: [Common 17-206] Exiting Vivado at Thu Jul 30 17:41:30 2020...
mkdir -p ./build_dir.hw.xilinx_u280_xdma_201920_3
v++ -t hw --platform /opt/xilinx/platforms/xilinx_u280_xdma_201920_3/xilinx_u280_xdma_201920_3.xpfm --save-temps --temp_dir ./build_dir.hw.xilinx_u280_xdma_201920_3 -l -o'build_dir.hw.xilinx_u280_xdma_201920_3/vadd.xclbin' _x.hw.xilinx_u280_xdma_201920_3/vadd.xo
Option Map File Used: '/opt/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'

INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
Reports: /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/reports/link
Log files: /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/logs/link
Running Dispatch Server on port:33003
INFO: [v++ 60-1548] Creating build summary session with primary output /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/vadd.xclbin.link_summary, at Thu Jul 30 17:41:57 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Thu Jul 30 17:41:57 2020
Running Rule Check Server on port:41231
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/reports/link/v++_link_vadd_guidance.html', at Thu Jul 30 17:41:58 2020
INFO: [v++ 60-895] Target platform: /opt/xilinx/platforms/xilinx_u280_xdma_201920_3/xilinx_u280_xdma_201920_3.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/opt/xilinx/platforms/xilinx_u280_xdma_201920_3/hw/xilinx_u280_xdma_201920_3.xsa'
INFO: [v++ 60-629] Linking for hardware target
INFO: [v++ 60-423] Target device: xilinx_u280_xdma_201920_3
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [17:42:04] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/_x.hw.xilinx_u280_xdma_201920_3/vadd.xo -keep --xpfm /opt/xilinx/platforms/xilinx_u280_xdma_201920_3/xilinx_u280_xdma_201920_3.xpfm --target hw --output_dir /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int --temp_dir /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link
INFO: [v++ 60-1454] Run Directory: /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/run_link
INFO: [SYSTEM_LINK 82-76] Reading emulation BD and HPFM information
INFO: [SYSTEM_LINK 60-1316] Initiating connection to rulecheck server, at Thu Jul 30 17:42:09 2020
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/_x.hw.xilinx_u280_xdma_201920_3/vadd.xo
INFO: [SYSTEM_LINK 82-53] Creating IP database /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [17:42:09] build_xd_ip_db started: /opt/Xilinx/Vitis/2019.2/bin/build_xd_ip_db -ip_search 0 -sds-pf /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/xilinx_u280_xdma_201920_3.hpfm -clkid 0 -ip /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/iprepo/xilinx_com_RTLKernel_krnl_vadd_rtl_1_0,krnl_vadd_rtl -o /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [17:42:15] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 295.672 ; gain = 0.000 ; free physical = 338885 ; free virtual = 457756
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [17:42:15] cfgen started: /opt/Xilinx/Vitis/2019.2/bin/cfgen -dmclkid 0 -r /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs:
INFO: [CFGEN 83-0] kernel: krnl_vadd_rtl, num: 1 {krnl_vadd_rtl_1}
INFO: [CFGEN 83-2226] Inferring mapping for argument krnl_vadd_rtl_1.a to HBM[0]
INFO: [CFGEN 83-2226] Inferring mapping for argument krnl_vadd_rtl_1.b to HBM[0]
INFO: [CFGEN 83-2226] Inferring mapping for argument krnl_vadd_rtl_1.c to HBM[0]
INFO: [SYSTEM_LINK 82-37] [17:42:21] cfgen finished successfully
Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 295.672 ; gain = 0.000 ; free physical = 338829 ; free virtual = 457699
INFO: [SYSTEM_LINK 82-52] Create top-level block diagram
INFO: [SYSTEM_LINK 82-38] [17:42:21] cf2bd started: /opt/Xilinx/Vitis/2019.2/bin/cf2bd --linux --trace_buffer 1024 --input_file /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/cfgraph/cfgen_cfgraph.xml --ip_db /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/_sysl/.cdb/xd_ip_db.xml --cf_name dr --working_dir /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/_sysl/.xsd --temp_dir /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link --output_dir /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int --target_bd pfm_dynamic.bd
INFO: [CF2BD 82-31] Launching cf2xd: cf2xd -linux -trace-buffer 1024 -i /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/cfgraph/cfgen_cfgraph.xml -r /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o dr.xml
INFO: [CF2BD 82-28] cf2xd finished successfully
INFO: [CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -bd pfm_dynamic.bd -dn dr -dp /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/_sysl/.xsd
INFO: [CF2BD 82-28] cf_xsd finished successfully
INFO: [SYSTEM_LINK 82-37] [17:42:23] cf2bd finished successfully
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 295.672 ; gain = 0.000 ; free physical = 346504 ; free virtual = 465379
INFO: [v++ 60-1441] [17:42:23] Run run_link: Step system_link: Completed
Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 679.508 ; gain = 0.000 ; free physical = 346522 ; free virtual = 465398
INFO: [v++ 60-1443] [17:42:23] Run run_link: Step cf2sw: Started
INFO: [v++ 60-1453] Command Line: cf2sw -sdsl /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/sdsl.dat -rtd /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/cf2sw.rtd -xclbin /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/xclbin_orig.xml -o /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/xclbin_orig.1.xml
INFO: [v++ 60-1454] Run Directory: /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/run_link
INFO: [v++ 60-1441] [17:42:25] Run run_link: Step cf2sw: Completed
Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 679.508 ; gain = 0.000 ; free physical = 346527 ; free virtual = 465402
INFO: [v++ 60-1443] [17:42:25] Run run_link: Step rtd2_system_diagram: Started
INFO: [v++ 60-1453] Command Line: rtd2SystemDiagram --rtdJsonFileName /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/cf2sw.rtd --diagramJsonFileName /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/systemDiagramModel.json --platformFilePath /opt/xilinx/platforms/xilinx_u280_xdma_201920_3/xilinx_u280_xdma_201920_3.xpfm --generatedByName v++ --generatedByVersion 2019.2 --generatedByChangeList 2708876 --generatedByTimeStamp Wed Nov 6 21:39:14 MST 2019 --generatedByOptions /opt/Xilinx/Vitis/2019.2/bin/unwrapped/lnx64.o/v++ -t hw --platform /opt/xilinx/platforms/xilinx_u280_xdma_201920_3/xilinx_u280_xdma_201920_3.xpfm --save-temps --temp_dir ./build_dir.hw.xilinx_u280_xdma_201920_3 -l -obuild_dir.hw.xilinx_u280_xdma_201920_3/vadd.xclbin _x.hw.xilinx_u280_xdma_201920_3/vadd.xo --generatedByXclbinName vadd --kernelInfoDataFileName /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/kernel_info.dat
INFO: [v++ 60-1454] Run Directory: /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/run_link
INFO: [v++ 60-839] Read in kernel information from file '/home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/kernel_info.dat'.
WARNING: [v++ 82-214] Could not generate kernel estimated resources because /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/xo/krnl_vadd_rtl/krnl_vadd_rtl/krnl_vadd_rtl.design.xml does not exist.
INFO: [v++ 60-1441] [17:42:26] Run run_link: Step rtd2_system_diagram: Completed
Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 679.508 ; gain = 0.000 ; free physical = 346526 ; free virtual = 465401
INFO: [v++ 60-1443] [17:42:26] Run run_link: Step vpl: Started
INFO: [v++ 60-1453] Command Line: vpl -t hw -f /opt/xilinx/platforms/xilinx_u280_xdma_201920_3/xilinx_u280_xdma_201920_3.xpfm -s --output_dir /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int --log_dir /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/logs/link --report_dir /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/reports/link --config /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/vplConfig.ini -k /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/kernel_info.dat --webtalk_flag Vitis --temp_dir /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link --no-info --tlog_dir /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/.tlog/v++_link_vadd --iprepo /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/xo/ip_repo/xilinx_com_RTLKernel_krnl_vadd_rtl_1_0 --messageDb /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/run_link/vpl.pb /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/dr.bd.tcl
INFO: [v++ 60-1454] Run Directory: /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/run_link

INFO: [VPL 60-839] Read in kernel information from file '/home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/kernel_info.dat'.
INFO: [VPL 60-423] Target device: xilinx_u280_xdma_201920_3
INFO: [VPL 60-1032] Extracting hardware platform to /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/vivado/vpl/.local/hw_platform
[17:43:23] Run vpl: Step create_project: Started
Creating Vivado project.
[17:43:25] Run vpl: Step create_project: Completed
[17:43:25] Run vpl: Step create_bd: Started
[17:44:46] Run vpl: Step create_bd: Completed
[17:44:46] Run vpl: Step update_bd: Started
[17:45:14] Run vpl: Step update_bd: Completed
[17:45:14] Run vpl: Step generate_target: Started
[17:46:15] Run vpl: Step generate_target: Completed
[17:46:15] Run vpl: Step config_hw_runs: Started
[17:46:18] Run vpl: Step config_hw_runs: Completed
[17:46:18] Run vpl: Step synth: Started
[17:46:53] Block-level synthesis in progress, 0 of 5 jobs complete, 4 jobs running.
[17:47:27] Block-level synthesis in progress, 0 of 5 jobs complete, 4 jobs running.
[17:48:02] Block-level synthesis in progress, 0 of 5 jobs complete, 4 jobs running.
[17:48:36] Block-level synthesis in progress, 3 of 5 jobs complete, 1 job running.
[17:49:11] Block-level synthesis in progress, 4 of 5 jobs complete, 0 jobs running.
[17:49:45] Block-level synthesis in progress, 4 of 5 jobs complete, 1 job running.
[17:50:20] Block-level synthesis in progress, 4 of 5 jobs complete, 1 job running.
[17:50:53] Block-level synthesis in progress, 4 of 5 jobs complete, 1 job running.
[17:51:28] Top-level synthesis in progress.
[17:52:02] Top-level synthesis in progress.
[17:52:37] Top-level synthesis in progress.
[17:53:00] Run vpl: Step synth: Completed
[17:53:00] Run vpl: Step impl: Started
[17:58:23] Finished 2nd of 6 tasks (FPGA linking synthesized kernels to platform). Elapsed time: 00h 15m 55s

[17:58:23] Starting logic optimization..
[17:58:56] Phase 1 Retarget
[17:59:28] Phase 2 Constant propagation
[17:59:28] Phase 3 Sweep
[18:00:01] Phase 4 BUFG optimization
[18:00:01] Phase 5 Shift Register Optimization
[18:00:01] Phase 6 Post Processing Netlist
[18:00:33] Finished 3rd of 6 tasks (FPGA logic optimization). Elapsed time: 00h 02m 10s

[18:00:33] Starting logic placement..
[18:01:06] Phase 1 Placer Initialization
[18:01:06] Phase 1.1 Placer Initialization Netlist Sorting
[18:03:16] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
[18:04:21] Phase 1.3 Build Placer Netlist Model
[18:05:26] Phase 1.4 Constrain Clocks/Macros
[18:05:26] Phase 2 Global Placement
[18:05:26] Phase 2.1 Floorplanning
[18:06:31] Phase 2.2 Global Placement Core
/opt/Xilinx/Vitis/2019.2/bin/loader: line 280: 72377 Segmentation fault "$RDI_PROG" "$@"
INFO: [v++ 60-1442] [18:07:21] Run run_link: Step vpl: Failed
Time (s): cpu = 00:00:22 ; elapsed = 00:24:55 . Memory (MB): peak = 679.508 ; gain = 0.000 ; free physical = 336846 ; free virtual = 457622
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
Makefile:98: recipe for target 'build_dir.hw.xilinx_u280_xdma_201920_3/vadd.xclbin' failed
make: *** [build_dir.hw.xilinx_u280_xdma_201920_3/vadd.xclbin] Error 1

How can I increase the width of axi control address in the shell?

Vitis_Accel_Examples/rtl_kernels/rtl_vadd/src/hdl/krnl_vadd_rtl.v

Line 45 in 9231c73

parameter integer C_S_AXI_CONTROL_ADDR_WIDTH = 6,

Cannot run PLRAM example on U280

Hi,

I got the following error when running PLRAM example in the repo. I got the following error from XRT

Device[1]: program successful!
Creating a kernel [test:{test_1}] for CU(1)
[XRT] ERROR: std::bad_alloc

My env:

Vitis 2019.2 +
U280 data center card

Any thoughts how to solve the bad alloc issue?

Same question posted on Xilinx forum: https://forums.xilinx.com/t5/Alveo-Accelerator-Cards/Cannot-run-bitstream-using-PLRAM-on-U280/td-p/1184694

hello_world and nimbix/jarvice

Hello,

I am trying to compile the hello_world example in Nimbix following instructions https://alveo.readthedocs.io/en/latest/vitis/.

To my surprise the compilation with

TMP_WORK_DIR=$(mktemp -d) && make -C /data/Vitis_Accel_Examples/hello_world all BUILD_DIR=${TMP_WORK_DIR} TARGET=hw DEVICE=xilinx_u200_xdma_201830_2 && cp ${TMP_WORK_DIR}/*.xclbin /data/Vitis_Accel_Examples/hello_world

I get :

INFO: [v++ 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
ERROR: [v++ 200-61] /data/Vitis_Accel_Examples/hello_world/src/vadd.cpp:100: unsupported memory access on variable 'in1' which is (or contains) an array with unknown size at compile time.
ERROR: [v++ 200-70] Synthesizability check failed.
ERROR: [v++ 60-300] Failed to build kernel(ip) vadd, see log for details: /data/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u200_xdma_201830_2/vadd/vadd/vivado_hls.log
ERROR: [v++ 60-599] Kernel compilation failed to complete
ERROR: [v++ 60-592] Failed to finish compilation

Is there a problem with this simple example in Nimbix?

I tried also with the kmeans example but it also failed with a different error:

ERROR: [CF2BD 82-34] cf_xsd: Failed to generate design file: dr.bd.tcl
ERROR: [SYSTEM_LINK 82-36] [07:24:19] cf2bd failed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 180.418 ; gain = 0.000 ; free physical = 63829 ; free virtual = 196380
ERROR: [SYSTEM_LINK 82-61] Error generating design file dr.bd.tcl
ERROR: [SYSTEM_LINK 82-80] Unable to create top-level block diagram
INFO: [v++ 60-1442] [07:24:19] Run run_link: Step system_link: Failed
Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 561.820 ; gain = 0.000 ; free physical = 63848 ; free virtual = 196399
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
Makefile:115: recipe for target '/tmp/tmp.FzMt2iMNkW/krnl_kmeans.xclbin' failed
make: *** [/tmp/tmp.FzMt2iMNkW/krnl_kmeans.xclbin] Error 1
make: Leaving directory '/data/Vitis_Accel_Examples/demo/kmeans'

v++: Command not found

Hi,
When I want to make the hello_world example, I get these tips
g++ -o hello_world /home/fpgauser/fpga_code/Vitis_Accel_Examples-master/common/includes/xcl2/xcl2.cpp src/host.cpp -I/opt/xilinx/xrt/include -I/include -Wall -O0 -g -std=c++1y -I/home/fpgauser/fpga_code/Vitis_Accel_Examples-master/common/includes/xcl2 -fmessage-length=0 -L/opt/xilinx/xrt/lib -lOpenCL -pthread -lrt -lstdc++

mkdir -p ./_x.sw_emu.xilinx_u200_xdma_201830_2

v++ -t sw_emu --platform xilinx_u200_xdma_201830_2 --save-temps -g -c -k vadd --temp_dir ./_x.sw_emu.xilinx_u200_xdma_201830_2 -I'src' -o'_x.sw_emu.xilinx_u200_xdma_201830_2/vadd.xo' 'src/vadd.cpp'

make: v++: Command not found

Makefile:135: recipe for target '_x.sw_emu.xilinx_u200_xdma_201830_2/vadd.xo' failed

make: *** [_x.sw_emu.xilinx_u200_xdma_201830_2/vadd.xo] Error 127

My GCC version is GCC version 5.4.0 20160609 (Ubuntu 5.4.0-6ubuntu1~16.04.12)
Is V++ error due to my GCC version problem? If so, what is the minimum version of GCC?

Something About data_transfer

Hello,

When I was running the test code DATA_TRANSFER, I wanted to change the read file to another place and change the size of the read file. I found that the size created in the test example was:
204K dummy_kernel.xclbin
What should I do if I want to create the file somewhere else and change the file size?

Thanks,
Hundan

Examples not compiling in Vitis when copying manually

Using all the latest stuff from Xilinx, Xilinx Unified Installer 2021.2 including the patch released 6 January.

$ uname -rs
Linux 5.4.0-21-generic

$ lsb_release -a
No LSB modules are available.
Distributor ID: Ubuntu
Description: Ubuntu 20.04 LTS
Release: 20.04
Codename: focal

HW: U50

It seems that Vitis do not accept the examples if they are not installed via Vitis IDE.
Is it not possible to just copy the files into directory Vitis_examples ? Is some extra needed to be done?

Clone https://github.com/Xilinx/Vitis_Accel_Examples
Copy Vitis_Accel_Examples to usb stick
Copy Vitis_Accel_Examples from usb stick to target machine into the directory ~/.Xilinx/Vitis/201.2/Vitis_examples

Start Vitis
Create a project, slask2, based on Vitis_Example "Hello world"
Compile

This compilation will fail because the main program can not find xcl2.hpp

The xcl2 source files are placed in
~/.Xilinx/Vitis/201.2/Vitis_examples/Vitis_Accel_Examples/common/includes/xcl2

But this directory is not included in the "include" folder in the project,
nor is xcl2.hpp or xcl2.cpp copied to
~/workspace/slask2/src
~/workspace/slask2/Emulation-SW/src (This directory is empty)

Note, it is possible to compile and execute the project if the makefile system is used in a terminal window.

launch_waveform is not working on emulation

In Vitis 2020, ran rtl_kernel /rtl_vadd.
Created an xrt.ini
[Debug]
profile=true
launch_waveform=batch
[Runtime]
exclusive_cu_context=true

Test:
make check DEVICE=xilinx_u200_qdma_201920_1 TARGET=hw_emu

Issue: There is no waveform coming up nor there is full wdb database.

U200 Errors

Some errors have happened when I run "hello world" example
Vitis version:2020.1
And git clone 2020.1 version example

`make all TARGET=hw_emu DEVICE=xilinx_u200_xdma_201830_2 HOST_ARCH=x86
mkdir -p ./_x.hw_emu.xilinx_u200_xdma_201830_2
v++ -c -k vadd -t hw_emu --platform xilinx_u200_xdma_201830_2 --save-temps  -g --temp_dir ./_x.hw_emu.xilinx_u200_xdma_201830_2  -I'src' -o'_x.hw_emu.xilinx_u200_xdma_201830_2/vadd.xo' 'src/vadd.cpp'
Option Map File Used: '/tools/Xilinx/Vitis/2020.1/data/vitis/vpp/optMap.xml'

****** v++ v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
	Reports: /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/_x.hw_emu.xilinx_u200_xdma_201830_2/reports/vadd
	Log files: /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/_x.hw_emu.xilinx_u200_xdma_201830_2/logs/vadd
INFO: [v++ 60-1657] Initializing dispatch client.
Running Dispatch Server on port:35789
INFO: [v++ 60-1548] Creating build summary session with primary output /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/_x.hw_emu.xilinx_u200_xdma_201830_2/vadd.xo.compile_summary, at Fri Nov 19 13:20:35 2021
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Fri Nov 19 13:20:35 2021
Running Rule Check Server on port:40579
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/_x.hw_emu.xilinx_u200_xdma_201830_2/reports/vadd/v++_compile_vadd_guidance.html', at Fri Nov 19 13:20:36 2021
INFO: [v++ 60-895]   Target platform: /opt/xilinx/platforms/xilinx_u200_xdma_201830_2/xilinx_u200_xdma_201830_2.xpfm
INFO: [v++ 60-1578]   This platform contains Device Support Archive '/opt/xilinx/platforms/xilinx_u200_xdma_201830_2/hw/xilinx_u200_xdma_201830_2.dsa'
INFO: [v++ 60-1302] Platform 'xilinx_u200_xdma_201830_2.xpfm' has been explicitly enabled for this release.
INFO: [v++ 60-585] Compiling for hardware emulation target
INFO: [v++ 60-423]   Target device: xilinx_u200_xdma_201830_2
INFO: [v++ 60-242] Creating kernel: 'vadd'

===>The following messages were generated while  performing high-level synthesis for kernel: vadd Log file: /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/_x.hw_emu.xilinx_u200_xdma_201830_2/vadd/vadd/vitis_hls.log :
INFO: [v++ 204-61] Pipelining loop 'read1'.
INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'read2'.
INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'vadd'.
INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'write'.
INFO: [v++ 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [v++ 200-789] **** Estimated Fmax: 411.02 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/_x.hw_emu.xilinx_u200_xdma_201830_2/reports/vadd/system_estimate_vadd.xtxt
INFO: [v++ 60-586] Created _x.hw_emu.xilinx_u200_xdma_201830_2/vadd.xo
INFO: [v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command. 
    vitis_analyzer /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/_x.hw_emu.xilinx_u200_xdma_201830_2/vadd.xo.compile_summary 
INFO: [v++ 60-791] Total elapsed time: 0h 0m 38s
INFO: [v++ 60-1653] Closing dispatch client.
mkdir -p ./build_dir.hw_emu.xilinx_u200_xdma_201830_2
v++ -l  -t hw_emu --platform xilinx_u200_xdma_201830_2 --save-temps  -g --temp_dir ./build_dir.hw_emu.xilinx_u200_xdma_201830_2  -o'./build_dir.hw_emu.xilinx_u200_xdma_201830_2/vadd.link.xclbin' _x.hw_emu.xilinx_u200_xdma_201830_2/vadd.xo
Option Map File Used: '/tools/Xilinx/Vitis/2020.1/data/vitis/vpp/optMap.xml'

****** v++ v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
	Reports: /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/reports/link
	Log files: /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/logs/link
INFO: [v++ 60-1657] Initializing dispatch client.
Running Dispatch Server on port:45569
INFO: [v++ 60-1548] Creating build summary session with primary output /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/vadd.link.xclbin.link_summary, at Fri Nov 19 13:21:16 2021
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Fri Nov 19 13:21:16 2021
Running Rule Check Server on port:41119
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/reports/link/v++_link_vadd.link_guidance.html', at Fri Nov 19 13:21:17 2021
INFO: [v++ 60-895]   Target platform: /opt/xilinx/platforms/xilinx_u200_xdma_201830_2/xilinx_u200_xdma_201830_2.xpfm
INFO: [v++ 60-1578]   This platform contains Device Support Archive '/opt/xilinx/platforms/xilinx_u200_xdma_201830_2/hw/xilinx_u200_xdma_201830_2.dsa'
INFO: [v++ 60-1302] Platform 'xilinx_u200_xdma_201830_2.xpfm' has been explicitly enabled for this release.
INFO: [v++ 60-629] Linking for hardware emulation target
INFO: [v++ 60-423]   Target device: xilinx_u200_xdma_201830_2
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [13:21:23] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/_x.hw_emu.xilinx_u200_xdma_201830_2/vadd.xo -keep --xpfm /opt/xilinx/platforms/xilinx_u200_xdma_201830_2/xilinx_u200_xdma_201830_2.xpfm --target emu --output_dir /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int --temp_dir /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link
INFO: [v++ 60-1454] Run Directory: /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/run_link
INFO: [SYSTEM_LINK 60-1316] Initiating connection to rulecheck server, at Fri Nov 19 13:21:25 2021
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/_x.hw_emu.xilinx_u200_xdma_201830_2/vadd.xo
INFO: [SYSTEM_LINK 82-53] Creating IP database /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [13:21:25] build_xd_ip_db started: /tools/Xilinx/Vitis/2020.1/bin/build_xd_ip_db -ip_search 0  -sds-pf /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/emu/xilinx_u200_xdma_201830_2_emu.hpfm -clkid 0 -ip /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/iprepo/xilinx_com_hls_vadd_1_0,vadd -o /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [13:21:27] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1439.250 ; gain = 0.000 ; free physical = 823 ; free virtual = 3491
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [13:21:27] cfgen started: /tools/Xilinx/Vitis/2020.1/bin/cfgen -dmclkid 0 -r /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs: 
INFO: [CFGEN 83-0]   kernel: vadd, num: 1  {vadd_1}
INFO: [CFGEN 83-2226] Inferring mapping for argument vadd_1.in1 to DDR[1]
INFO: [CFGEN 83-2226] Inferring mapping for argument vadd_1.in2 to DDR[1]
INFO: [CFGEN 83-2226] Inferring mapping for argument vadd_1.out_r to DDR[1]
INFO: [SYSTEM_LINK 82-37] [13:21:29] cfgen finished successfully
Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1439.250 ; gain = 0.000 ; free physical = 782 ; free virtual = 3451
INFO: [SYSTEM_LINK 82-52] Create top-level block diagram
INFO: [SYSTEM_LINK 82-38] [13:21:29] cf2bd started: /tools/Xilinx/Vitis/2020.1/bin/cf2bd  --linux --trace_buffer 1024 --input_file /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/cfgraph/cfgen_cfgraph.xml --ip_db /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/_sysl/.cdb/xd_ip_db.xml --cf_name dr --working_dir /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/_sysl/.xsd --temp_dir /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link --output_dir /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int --target_bd emu/emu.bd
INFO: [CF2BD 82-31] Launching cf2xd: cf2xd -linux -trace-buffer 1024 -i /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/cfgraph/cfgen_cfgraph.xml -r /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o dr.xml
INFO: [CF2BD 82-28] cf2xd finished successfully
INFO: [CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -bd emu/emu.bd -dn dr -dp /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/sys_link/_sysl/.xsd
INFO: [CF2BD 82-28] cf_xsd finished successfully
INFO: [SYSTEM_LINK 82-37] [13:21:31] cf2bd finished successfully
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1439.250 ; gain = 0.000 ; free physical = 721 ; free virtual = 3413
INFO: [v++ 60-1441] [13:21:31] Run run_link: Step system_link: Completed
Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1346.410 ; gain = 0.000 ; free physical = 748 ; free virtual = 3440
INFO: [v++ 60-1443] [13:21:31] Run run_link: Step cf2sw: Started
INFO: [v++ 60-1453] Command Line: cf2sw -sdsl /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int/sdsl.dat -rtd /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int/cf2sw.rtd -xclbin /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int/xclbin_orig.xml -o /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int/xclbin_orig.1.xml
INFO: [v++ 60-1454] Run Directory: /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/run_link
INFO: [v++ 60-1441] [13:21:32] Run run_link: Step cf2sw: Completed
Time (s): cpu = 00:00:00.88 ; elapsed = 00:00:00.93 . Memory (MB): peak = 1346.410 ; gain = 0.000 ; free physical = 811 ; free virtual = 3503
INFO: [v++ 60-1443] [13:21:32] Run run_link: Step rtd2_system_diagram: Started
INFO: [v++ 60-1453] Command Line: rtd2SystemDiagram
INFO: [v++ 60-1454] Run Directory: /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/run_link
INFO: [v++ 60-1441] [13:21:33] Run run_link: Step rtd2_system_diagram: Completed
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.79 . Memory (MB): peak = 1346.410 ; gain = 0.000 ; free physical = 408 ; free virtual = 3105
INFO: [v++ 60-1443] [13:21:33] Run run_link: Step vpl: Started
INFO: [v++ 60-1453] Command Line: vpl -t hw_emu -f xilinx_u200_xdma_201830_2 -g --remote_ip_cache /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/.ipcache -s --output_dir /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int --log_dir /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/logs/link --report_dir /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/reports/link --config /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int/vplConfig.ini -k /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int/kernel_info.dat --webtalk_flag Vitis --temp_dir /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link --emulation_mode debug_waveform --no-info --iprepo /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int/xo/ip_repo/xilinx_com_hls_vadd_1_0 --messageDb /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/run_link/vpl.pb /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int/dr.bd.tcl
INFO: [v++ 60-1454] Run Directory: /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/run_link

****** vpl v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: [VPL 60-839] Read in kernel information from file '/home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/int/kernel_info.dat'.
INFO: [VPL 60-423]   Target device: xilinx_u200_xdma_201830_2
INFO: [VPL 60-1032] Extracting hardware platform to /home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/vivado/vpl/.local/hw_platform
[13:21:51] Run vpl: Step create_project: Started
Creating Vivado project.
[13:21:53] Run vpl: Step create_project: Completed
[13:21:53] Run vpl: Step create_bd: Started
[13:22:28] Run vpl: Step create_bd: Completed
[13:22:28] Run vpl: Step update_bd: Started
[13:22:30] Run vpl: Step update_bd: Completed
[13:22:30] Run vpl: Step generate_target: Started
[13:22:51] Run vpl: Step generate_target: Completed
[13:22:51] Run vpl: Step config_hw_emulation: Started
[13:24:10] Run vpl: Step config_hw_emulation: RUNNING...
[13:24:12] Run vpl: Step config_hw_emulation: Failed
[13:24:16] Run vpl: FINISHED. Run Status: config_hw_emulation ERROR
ERROR: [VPL 60-773] In '/home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/vivado/vpl/vivado.log', caught Tcl error:  ./elaborate.sh: line 20: LIBRARY_PATH: unbound variable
ERROR: [VPL 60-2373] In '/home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/vivado/vpl/vivado.log', caught error: ERROR: caught error: ./elaborate.sh: line 20: LIBRARY_PATH: unbound variable
ERROR: [VPL 60-2373] In '/home/enai/Desktop/project/enai0/Vitis_Accel_Examples-2020.1/hello_world/build_dir.hw_emu.xilinx_u200_xdma_201830_2/link/vivado/vpl/runme.log', caught error: ERROR: caught error: ./elaborate.sh: line 20: LIBRARY_PATH: unbound variable
ERROR: [VPL 60-1328] Vpl run 'vpl' failed
ERROR: [VPL 60-806] Failed to finish platform linker
INFO: [v++ 60-1442] [13:24:17] Run run_link: Step vpl: Failed
Time (s): cpu = 00:03:51 ; elapsed = 00:02:44 . Memory (MB): peak = 1346.410 ; gain = 0.000 ; free physical = 3835 ; free virtual = 5704
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
INFO: [v++ 60-1653] Closing dispatch client.
Makefile:120: recipe for target 'build_dir.hw_emu.xilinx_u200_xdma_201830_2/vadd.xclbin' failed
make: *** [build_dir.hw_emu.xilinx_u200_xdma_201830_2/vadd.xclbin] Error 1
`

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For this project: Vitis_Accel_Examples/sys_opt/multiple_process/ When bulid the project from command line: the three xo files can be generated, but during the link stage, error report:

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For this project: Vitis_Accel_Examples/sys_opt/multiple_process/
When bulid the project from command line: the three xo files can be generated, but during the link stage, error report: