Hi, I was building the rtl_vadd example code with 2019.2 branch and there is segmentation fault error.
The detail command and the log output is the following:
make all TARGET=hw DEVICE=/opt/xilinx/platforms/xilinx_u280_xdma_201920_3/xilinx_u280_xdma_201920_3.xpfm
g++ -I../..//common/includes/xcl2 -I/opt/xilinx/xrt/include -I/opt/Xilinx/Vivado/2019.2/include -Wall -O0 -g -std=c++11 -fmessage-length=0 ../..//common/includes/xcl2/xcl2.cpp src/host.cpp -o 'host' -L/opt/xilinx/xrt/lib -lOpenCL -lpthread -lrt -lstdc++
mkdir -p ./_x.hw.xilinx_u280_xdma_201920_3
/opt/Xilinx/Vivado/2019.2/bin/vivado -mode batch -source scripts/gen_xo.tcl -tclargs ./_x.hw.xilinx_u280_xdma_201920_3/vadd.xo vadd hw /opt/xilinx/platforms/xilinx_u280_xdma_201920_3/xilinx_u280_xdma_201920_3.xpfm xilinx_u280_xdma_201920_3
****** Vivado v2019.2 (64-bit)
**** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
**** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
source scripts/gen_xo.tcl
INFO: [IP_Flow 19-5169] Module 'krnl_vadd_rtl' uses SystemVerilog sources with a Verilog top file. These SystemVerilog files will not be analysed by the packager.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_gmem' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_control' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'interrupt' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'ap_rst_n': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'interrupt': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'ap_rst_n'.
WARNING: [IP_Flow 19-3158] Bus Interface 'm_axi_gmem': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 's_axi_control': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3157] Bus Interface 'ap_rst_n': Bus parameter POLARITY is ACTIVE_LOW but port 'ap_rst_n' is not *resetn - please double check the POLARITY setting.
WARNING: [IP_Flow 19-3153] Bus Interface 'ap_clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [IP_Flow 19-795] Syncing license key meta-data
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/packaged_kernel_vadd_hw_xilinx_u280_xdma_201920_3/src/krnl_vadd_rtl_control_s_axi.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/packaged_kernel_vadd_hw_xilinx_u280_xdma_201920_3/src/krnl_vadd_rtl_adder.sv:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/packaged_kernel_vadd_hw_xilinx_u280_xdma_201920_3/src/krnl_vadd_rtl_axi_read_master.sv:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/packaged_kernel_vadd_hw_xilinx_u280_xdma_201920_3/src/krnl_vadd_rtl_axi_write_master.sv:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/packaged_kernel_vadd_hw_xilinx_u280_xdma_201920_3/src/krnl_vadd_rtl_counter.sv:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/packaged_kernel_vadd_hw_xilinx_u280_xdma_201920_3/src/krnl_vadd_rtl_int.sv:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/packaged_kernel_vadd_hw_xilinx_u280_xdma_201920_3/src/krnl_vadd_rtl.v:]
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axi_gmem'.
WARNING: [IP_Flow 19-3157] Bus Interface 'ap_rst_n': Bus parameter POLARITY is ACTIVE_LOW but port 'ap_rst_n' is not *resetn - please double check the POLARITY setting.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed.
WARNING: [Vivado 12-4404] The CPU emulation flow in v++ is only supported when using a packaged XO file that contains C-model files, none were found.
WARNING: [Vivado 12-7038] The bus parameter 'ap_clk.FREQ_HZ' has been detected in the kernel IP 'krnl_vadd_rtl'. This may cause validation errors in v++ if a target platform has a different default kernel clock frequency. If validation errors do occur in v++, please edit and re-generate the kernel IP 'krnl_vadd_rtl' to remove the bus parameter 'ap_clk.FREQ_HZ'
INFO: [Common 17-206] Exiting Vivado at Thu Jul 30 17:41:30 2020...
mkdir -p ./build_dir.hw.xilinx_u280_xdma_201920_3
v++ -t hw --platform /opt/xilinx/platforms/xilinx_u280_xdma_201920_3/xilinx_u280_xdma_201920_3.xpfm --save-temps --temp_dir ./build_dir.hw.xilinx_u280_xdma_201920_3 -l -o'build_dir.hw.xilinx_u280_xdma_201920_3/vadd.xclbin' _x.hw.xilinx_u280_xdma_201920_3/vadd.xo
Option Map File Used: '/opt/Xilinx/Vitis/2019.2/data/vitis/vpp/optMap.xml'
****** v++ v2019.2 (64-bit)
**** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
Reports: /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/reports/link
Log files: /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/logs/link
Running Dispatch Server on port:33003
INFO: [v++ 60-1548] Creating build summary session with primary output /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/vadd.xclbin.link_summary, at Thu Jul 30 17:41:57 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Thu Jul 30 17:41:57 2020
Running Rule Check Server on port:41231
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/reports/link/v++_link_vadd_guidance.html', at Thu Jul 30 17:41:58 2020
INFO: [v++ 60-895] Target platform: /opt/xilinx/platforms/xilinx_u280_xdma_201920_3/xilinx_u280_xdma_201920_3.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/opt/xilinx/platforms/xilinx_u280_xdma_201920_3/hw/xilinx_u280_xdma_201920_3.xsa'
INFO: [v++ 60-629] Linking for hardware target
INFO: [v++ 60-423] Target device: xilinx_u280_xdma_201920_3
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [17:42:04] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/_x.hw.xilinx_u280_xdma_201920_3/vadd.xo -keep --xpfm /opt/xilinx/platforms/xilinx_u280_xdma_201920_3/xilinx_u280_xdma_201920_3.xpfm --target hw --output_dir /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int --temp_dir /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link
INFO: [v++ 60-1454] Run Directory: /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/run_link
INFO: [SYSTEM_LINK 82-76] Reading emulation BD and HPFM information
INFO: [SYSTEM_LINK 60-1316] Initiating connection to rulecheck server, at Thu Jul 30 17:42:09 2020
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/_x.hw.xilinx_u280_xdma_201920_3/vadd.xo
INFO: [SYSTEM_LINK 82-53] Creating IP database /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [17:42:09] build_xd_ip_db started: /opt/Xilinx/Vitis/2019.2/bin/build_xd_ip_db -ip_search 0 -sds-pf /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/xilinx_u280_xdma_201920_3.hpfm -clkid 0 -ip /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/iprepo/xilinx_com_RTLKernel_krnl_vadd_rtl_1_0,krnl_vadd_rtl -o /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [17:42:15] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 295.672 ; gain = 0.000 ; free physical = 338885 ; free virtual = 457756
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [17:42:15] cfgen started: /opt/Xilinx/Vitis/2019.2/bin/cfgen -dmclkid 0 -r /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs:
INFO: [CFGEN 83-0] kernel: krnl_vadd_rtl, num: 1 {krnl_vadd_rtl_1}
INFO: [CFGEN 83-2226] Inferring mapping for argument krnl_vadd_rtl_1.a to HBM[0]
INFO: [CFGEN 83-2226] Inferring mapping for argument krnl_vadd_rtl_1.b to HBM[0]
INFO: [CFGEN 83-2226] Inferring mapping for argument krnl_vadd_rtl_1.c to HBM[0]
INFO: [SYSTEM_LINK 82-37] [17:42:21] cfgen finished successfully
Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 295.672 ; gain = 0.000 ; free physical = 338829 ; free virtual = 457699
INFO: [SYSTEM_LINK 82-52] Create top-level block diagram
INFO: [SYSTEM_LINK 82-38] [17:42:21] cf2bd started: /opt/Xilinx/Vitis/2019.2/bin/cf2bd --linux --trace_buffer 1024 --input_file /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/cfgraph/cfgen_cfgraph.xml --ip_db /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/_sysl/.cdb/xd_ip_db.xml --cf_name dr --working_dir /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/_sysl/.xsd --temp_dir /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link --output_dir /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int --target_bd pfm_dynamic.bd
INFO: [CF2BD 82-31] Launching cf2xd: cf2xd -linux -trace-buffer 1024 -i /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/cfgraph/cfgen_cfgraph.xml -r /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o dr.xml
INFO: [CF2BD 82-28] cf2xd finished successfully
INFO: [CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -bd pfm_dynamic.bd -dn dr -dp /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/sys_link/_sysl/.xsd
INFO: [CF2BD 82-28] cf_xsd finished successfully
INFO: [SYSTEM_LINK 82-37] [17:42:23] cf2bd finished successfully
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 295.672 ; gain = 0.000 ; free physical = 346504 ; free virtual = 465379
INFO: [v++ 60-1441] [17:42:23] Run run_link: Step system_link: Completed
Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 679.508 ; gain = 0.000 ; free physical = 346522 ; free virtual = 465398
INFO: [v++ 60-1443] [17:42:23] Run run_link: Step cf2sw: Started
INFO: [v++ 60-1453] Command Line: cf2sw -sdsl /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/sdsl.dat -rtd /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/cf2sw.rtd -xclbin /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/xclbin_orig.xml -o /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/xclbin_orig.1.xml
INFO: [v++ 60-1454] Run Directory: /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/run_link
INFO: [v++ 60-1441] [17:42:25] Run run_link: Step cf2sw: Completed
Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 679.508 ; gain = 0.000 ; free physical = 346527 ; free virtual = 465402
INFO: [v++ 60-1443] [17:42:25] Run run_link: Step rtd2_system_diagram: Started
INFO: [v++ 60-1453] Command Line: rtd2SystemDiagram --rtdJsonFileName /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/cf2sw.rtd --diagramJsonFileName /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/systemDiagramModel.json --platformFilePath /opt/xilinx/platforms/xilinx_u280_xdma_201920_3/xilinx_u280_xdma_201920_3.xpfm --generatedByName v++ --generatedByVersion 2019.2 --generatedByChangeList 2708876 --generatedByTimeStamp Wed Nov 6 21:39:14 MST 2019 --generatedByOptions /opt/Xilinx/Vitis/2019.2/bin/unwrapped/lnx64.o/v++ -t hw --platform /opt/xilinx/platforms/xilinx_u280_xdma_201920_3/xilinx_u280_xdma_201920_3.xpfm --save-temps --temp_dir ./build_dir.hw.xilinx_u280_xdma_201920_3 -l -obuild_dir.hw.xilinx_u280_xdma_201920_3/vadd.xclbin _x.hw.xilinx_u280_xdma_201920_3/vadd.xo --generatedByXclbinName vadd --kernelInfoDataFileName /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/kernel_info.dat
INFO: [v++ 60-1454] Run Directory: /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/run_link
INFO: [v++ 60-839] Read in kernel information from file '/home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/kernel_info.dat'.
WARNING: [v++ 82-214] Could not generate kernel estimated resources because /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/xo/krnl_vadd_rtl/krnl_vadd_rtl/krnl_vadd_rtl.design.xml does not exist.
INFO: [v++ 60-1441] [17:42:26] Run run_link: Step rtd2_system_diagram: Completed
Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 679.508 ; gain = 0.000 ; free physical = 346526 ; free virtual = 465401
INFO: [v++ 60-1443] [17:42:26] Run run_link: Step vpl: Started
INFO: [v++ 60-1453] Command Line: vpl -t hw -f /opt/xilinx/platforms/xilinx_u280_xdma_201920_3/xilinx_u280_xdma_201920_3.xpfm -s --output_dir /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int --log_dir /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/logs/link --report_dir /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/reports/link --config /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/vplConfig.ini -k /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/kernel_info.dat --webtalk_flag Vitis --temp_dir /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link --no-info --tlog_dir /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/.tlog/v++_link_vadd --iprepo /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/xo/ip_repo/xilinx_com_RTLKernel_krnl_vadd_rtl_1_0 --messageDb /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/run_link/vpl.pb /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/dr.bd.tcl
INFO: [v++ 60-1454] Run Directory: /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/run_link
****** vpl v2019.2 (64-bit)
**** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [VPL 60-839] Read in kernel information from file '/home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/int/kernel_info.dat'.
INFO: [VPL 60-423] Target device: xilinx_u280_xdma_201920_3
INFO: [VPL 60-1032] Extracting hardware platform to /home/zhe/Vitis_Accel_Examples/rtl_kernels/rtl_vadd/build_dir.hw.xilinx_u280_xdma_201920_3/link/vivado/vpl/.local/hw_platform
[17:43:23] Run vpl: Step create_project: Started
Creating Vivado project.
[17:43:25] Run vpl: Step create_project: Completed
[17:43:25] Run vpl: Step create_bd: Started
[17:44:46] Run vpl: Step create_bd: Completed
[17:44:46] Run vpl: Step update_bd: Started
[17:45:14] Run vpl: Step update_bd: Completed
[17:45:14] Run vpl: Step generate_target: Started
[17:46:15] Run vpl: Step generate_target: Completed
[17:46:15] Run vpl: Step config_hw_runs: Started
[17:46:18] Run vpl: Step config_hw_runs: Completed
[17:46:18] Run vpl: Step synth: Started
[17:46:53] Block-level synthesis in progress, 0 of 5 jobs complete, 4 jobs running.
[17:47:27] Block-level synthesis in progress, 0 of 5 jobs complete, 4 jobs running.
[17:48:02] Block-level synthesis in progress, 0 of 5 jobs complete, 4 jobs running.
[17:48:36] Block-level synthesis in progress, 3 of 5 jobs complete, 1 job running.
[17:49:11] Block-level synthesis in progress, 4 of 5 jobs complete, 0 jobs running.
[17:49:45] Block-level synthesis in progress, 4 of 5 jobs complete, 1 job running.
[17:50:20] Block-level synthesis in progress, 4 of 5 jobs complete, 1 job running.
[17:50:53] Block-level synthesis in progress, 4 of 5 jobs complete, 1 job running.
[17:51:28] Top-level synthesis in progress.
[17:52:02] Top-level synthesis in progress.
[17:52:37] Top-level synthesis in progress.
[17:53:00] Run vpl: Step synth: Completed
[17:53:00] Run vpl: Step impl: Started
[17:58:23] Finished 2nd of 6 tasks (FPGA linking synthesized kernels to platform). Elapsed time: 00h 15m 55s
[17:58:23] Starting logic optimization..
[17:58:56] Phase 1 Retarget
[17:59:28] Phase 2 Constant propagation
[17:59:28] Phase 3 Sweep
[18:00:01] Phase 4 BUFG optimization
[18:00:01] Phase 5 Shift Register Optimization
[18:00:01] Phase 6 Post Processing Netlist
[18:00:33] Finished 3rd of 6 tasks (FPGA logic optimization). Elapsed time: 00h 02m 10s
[18:00:33] Starting logic placement..
[18:01:06] Phase 1 Placer Initialization
[18:01:06] Phase 1.1 Placer Initialization Netlist Sorting
[18:03:16] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
[18:04:21] Phase 1.3 Build Placer Netlist Model
[18:05:26] Phase 1.4 Constrain Clocks/Macros
[18:05:26] Phase 2 Global Placement
[18:05:26] Phase 2.1 Floorplanning
[18:06:31] Phase 2.2 Global Placement Core
/opt/Xilinx/Vitis/2019.2/bin/loader: line 280: 72377 Segmentation fault "$RDI_PROG" "$@"
INFO: [v++ 60-1442] [18:07:21] Run run_link: Step vpl: Failed
Time (s): cpu = 00:00:22 ; elapsed = 00:24:55 . Memory (MB): peak = 679.508 ; gain = 0.000 ; free physical = 336846 ; free virtual = 457622
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
Makefile:98: recipe for target 'build_dir.hw.xilinx_u280_xdma_201920_3/vadd.xclbin' failed
make: *** [build_dir.hw.xilinx_u280_xdma_201920_3/vadd.xclbin] Error 1