ucb-bar / chipyard Goto Github PK

Would be nice to have a target that would rm -rf all the targets in the sbt projects.

Hi, I clone the latest version from master branch at 2017.1.17.
Then I follow the README.md part to build emulator. However, it fails with some errors happen.
error message:
/project-template/testchipip/csrc/SimSerial.cc: In function ‘int serial_tick(unsigned char, unsigned char*, int, unsigned char*, unsigned char, int*)’:
/project-template/testchipip/csrc/SimSerial.cc:26:87: error: no matching function for call to ‘tsi_t::tsi_t(std::vector<std::basic_string >)’
tsi = new tsi_t(std::vectorstd::string(info.argv + 1, info.argv + info.argc));
^
/project-template/testchipip/csrc/SimSerial.cc:26:87: note: candidate is:
In file included from /project-template/testchipip/csrc/SimSerial.cc:5:0:
/project-template/rocket-chip/riscv-tools/include/fesvr/tsi.h:21:3: note: tsi_t::tsi_t(int, char**)
tsi_t(int argc, char** argv);
^
/project-template/rocket-chip/riscv-tools/include/fesvr/tsi.h:21:3: note: candidate expects 2 arguments, 1 provided
make[1]: *** [SimSerial.o] Error 1
make[1]: *** Waiting for unfinished jobs....
/project-template/testchipip/csrc/verilator-harness.cc: In function ‘int main(int, char**)’:
/project-template/testchipip/csrc/verilator-harness.cc:84:66: error: no matching function for call to ‘tsi_t::tsi_t(std::vector<std::basic_string >)’
tsi = new tsi_t(std::vectorstd::string(argv + 1, argv + argc));
^
/project-template/testchipip/csrc/verilator-harness.cc:84:66: note: candidate is:
In file included from /project-template/testchipip/csrc/verilator-harness.cc:7:0:
/project-template/rocket-chip/riscv-tools/include/fesvr/tsi.h:21:3: note: tsi_t::tsi_t(int, char**)
tsi_t(int argc, char** argv);
^
/project-template/rocket-chip/riscv-tools/include/fesvr/tsi.h:21:3: note: candidate expects 2 arguments, 1 provided
make[1]: *** [verilator-harness.o] Error 1
make[1]: Leaving directory `/project-template/verisim/generated-src/example.TestHarness.PWMConfig'
make: *** [/project-template/verisim/simulator-example-PWMConfig] Error 2

It seems the code verilator-harness.cc and SimSerial.cc in testchip/csrc exist some code syntax mismatch from riscv-tools/include/fesvr/tsi.h. I am not familiar with the section.
Could anyone helps me about it?

Hi, When I am trying to add any block for example run make PROJECT=blkdev CONFIG=BlockDeviceConfig in the "verisim" directory, something goes wrong. The same issue i am facing for create own project & MIMO.

[info] Running blkdev.Generator /nfs/iind/disks/i2r.disk.0001/RISCV_Evaluation/Free-chip_project/rocket-radha/project-template/verisim/generated-src blkdev TestHarness blkdev BlockDeviceConfig
[error] (run-main-0) java.lang.ClassNotFoundException: blkdev.Generator

Hello all,
I'm trying to add JTAG debug module to the default example to use remote bitbang (debug with GDB) but when I try to build the emulator some error about jtag_tick shows in the terminal with "make" or "make debug" like the following one:

g++    SimBlockDevice.o SimSerial.o blkdev.o verilator-harness.o verilated.o verilated_dpi.o verilated_vcd_c.o VTestHarness__ALL.a   -L/home/aignacio/riscv-tools/lib -Wl,-rpath,/home/aignacio/riscv-tools/lib -L/home/aignacio/build/demo/verisim -lfesvr -lpthread  -o /home/aignacio/build/demo/verisim/simulator-example-DefaultExampleConfig-debug -lm -lstdc++ 
VTestHarness__ALL.a(VTestHarness___024unit.o): In function `VTestHarness___024unit::__Vdpiimwrap_jtag_tick_TOP____024unit(unsigned char&, unsigned char&, unsigned char&, unsigned char&, unsigned char, unsigned int&)':
VTestHarness___024unit.cpp:(.text+0x89): undefined reference to `jtag_tick'
collect2: error: ld returned 1 exit status
VTestHarness.mk:76: recipe for target '/home/aignacio/build/demo/verisim/simulator-example-DefaultExampleConfig-debug' failed
make[1]: *** [/home/aignacio/build/demo/verisim/simulator-example-DefaultExampleConfig-debug] Error 1
make[1]: Leaving directory '/home/aignacio/build/demo/verisim/generated-src/example.TestHarness.DefaultExampleConfig.debug'
Makefile:66: recipe for target '/home/aignacio/build/demo/verisim/simulator-example-DefaultExampleConfig-debug' failed
make: *** [/home/aignacio/build/demo/verisim/simulator-example-DefaultExampleConfig-debug] Error 2

I modified the TestHarness class with the following code:

#TestHarness.scala
#I ommited the other parts because it's actually the same thing
import freechips.rocketchip.devices.debug.Debug
...
...
...
class TestHarness(implicit val p: Parameters) extends Module {
  val io = IO(new Bundle {
    val success = Output(Bool())
  })

  val dut = p(BuildTop)(clock, reset.toBool, p)
//   dut.debug := DontCare
  dut.reset := reset.toBool || dut.debug.ndreset
  dut.connectSimAXIMem()
  dut.dontTouchPorts()
  dut.tieOffInterrupts()
  io.success := dut.connectSimSerial()
  Debug.connectDebug(dut.debug, clock, reset.toBool, io.success)
}

and in the packge example:

# Configs.scala
import freechips.rocketchip.subsystem.{WithJtagDTM, WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32}
...
...
...
class BaseExampleConfig extends Config(
  new WithBootROM ++
  new WithJtagDTM ++
  new freechips.rocketchip.system.DefaultConfig)

I'm using the same pattern as present in TestHarness from RocketChip repo and AFAIK the only difference it's the chisel3 package that now uses different casting for reset. Could someone please advice me how exactly I should add jtag interface into the example? Thanks!

Ps.: same behavior if I use the package WithJtagDTMSystem

Greetings,

Intro: I've used an old branch of fpga-zynq (f03982e) repository and added a version of project-template's PWM from around that time (27bd063) to the design. The reason I used such an old commit of fpga-zynq is because the newer branches aren't working for a some people, including me on ZC706. And to match that version of rocket-chip I also needed an older version of project-template.

Problem: If I did everything correctly, the PWM device was properly added to the design. I used the provided pwm.c code to test if I could write to the registers at the specified addresses:

#define PWM_PERIOD 0x2000
#define PWM_DUTY 0x2004
#define PWM_ENABLE 0x2008

#include "mmio.h"
#include <stdio.h>
#include <inttypes.h>

int main(void)
{
	reg_write32(PWM_PERIOD, 20);
	reg_write32(PWM_DUTY, 5);
	reg_write32(PWM_ENABLE, 1);

	printf("PWM_PERIOD = %" PRId32 "\n", reg_read32(PWM_PERIOD));
	printf("PWM_DUTY = %" PRId32 "\n", reg_read32(PWM_DUTY));
	printf("PWM_ENABLE = %" PRId32 "\n", reg_read32(PWM_ENABLE));

	return 0;
}

Writing to the registers returned no errors. However, when trying to read the registers after writing to them, they all return 0 as the current value.

I thought the registers would hold the values until they were re-written. If that is the case, do you have any idea where the problem may be coming from? If not, is there any simple way to make the registers hold the values? Does this happen because it's memory-mapped IO?

Don't know if it's relevant but I'm running pwm.riscv on the FPGA using fesvr-zynq.

Thanks in advance,

TL,DR: Is project-template/bootrom a testchipip construct?

I'm wondering what is the difference between the bootrom in top-level project-template and rocket-chip.

AFAICT, Rocket-chip's bootrom is built to use its rocket-chip/csrc/SimDTM.cc interface. It seems the project-template bootrom is build for the SimSerial from testchipip? If that is the case, that seems to suggest the project-template/bootrom should be moved to the testchipip repository.

Or is it more generic?

I made the pwm example, but now I want to get the peripherical signal in the TestHarness, how to do it?

class TestHarness(implicit val p: Parameters) extends Module {
  val io = IO(new Bundle {
    val success = Output(Bool())
    val output_perip = Output(Bool())
  })
  val dut = p(BuildTop)(clock, reset.toBool, p)
  dut.debug := DontCare
  dut.connectSimAXIMem()
  dut.dontTouchPorts()
  dut.tieOffInterrupts()
  io.success := dut.connectSimSerial()

  io.output_perip := io_pwmout // ?? Here 
}

I wanted my io.output_perip in this module:

Thanks!

Instead of running a whole project of rocket-chip, I wonder if it is possible to just emit a minimal AXI4 Module for PWM, which is much easier to evaluate by Xilinx ZYNQ FPGAs or simply used as DUT for testing.

I'm currently working on a university project. But im struggling with adding my one device to the Chip.
For the project I need to get a pwm working, which is a nice coincidence.
Anyway with the current state of the Rocket-Chip, the tutorial is not working.
I understand that the rocket-chip is transitioning from TileLinkIO to TileLinkIO2 atm, so it's probably not the best idea to updated the Tutorial right now.
But like I said we are struggling to make it work, so any help or information would be very much appreciated.

This line and this one have TL in the names, but nothing they do is TL specific. You could use them for an AXI-flavored PWM, for example. The names should reflect this.

i got FIRRTL ERROR when i try "make CONFIG=PWMConfig"

java -Xmx8G -Xss8M -cp "/mnt/e/Project/project-template/rocket-chip/target/scala-2.12/classes:/mnt/e/Project/project-template/rocket-chip/chisel3/target/scala-2.12/*":"/mnt/e/Project/project-template/testchipip/target/scala-2.12/classes":/mnt/e/Project/project-template/barstools/tapeout/target/scala-2.12/tapeout-assembly-1.0.jar barstools.tapeout.transforms.GenerateTop -o /mnt/e/Project/project-template/verisim/generated-src/example.TestHarness.PWMConfig.top.v -i /mnt/e/Project/project-template/verisim/generated-src/example.TestHarness.PWMConfig.fir --syn-top ExampleTop --harness-top TestHarness -faf /mnt/e/Project/project-template/verisim/generated-src/example.TestHarness.PWMConfig.anno.json --repl-seq-mem -c:TestHarness:-o:/mnt/e/Project/project-template/verisim/generated-src/example.TestHarness.PWMConfig.mems.conf -td /mnt/e/Project/project-template/verisim/generated-src
Exception in thread "main" firrtl.FIRRTLException: Internal Error! Please file an issue at https://github.com/ucb-bar/firrtl/issues
at firrtl.Utils$.error(Utils.scala:440)
at firrtl.Utils$.throwInternalError(Utils.scala:181)
at firrtl.Driver$.$anonfun$execute$1(Driver.scala:252)
at logger.Logger$.$anonfun$makeScope$2(Logger.scala:138)
at scala.util.DynamicVariable.withValue(DynamicVariable.scala:58)
at logger.Logger$.makeScope(Logger.scala:136)
at firrtl.Driver$.execute(Driver.scala:224)
at barstools.tapeout.transforms.GenerateTopAndHarnessApp.executeTop(Generate.scala:102)
at barstools.tapeout.transforms.GenerateTopAndHarnessApp.executeTop$(Generate.scala:96)
at barstools.tapeout.transforms.GenerateTop$.executeTop(Generate.scala:116)
at barstools.tapeout.transforms.GenerateTop$.delayedEndpoint$barstools$tapeout$transforms$GenerateTop$1(Generate.scala:118)
at barstools.tapeout.transforms.GenerateTop$delayedInit$body.apply(Generate.scala:116)
at scala.Function0.apply$mcV$sp(Function0.scala:34)
at scala.Function0.apply$mcV$sp$(Function0.scala:34)
at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:12)
at scala.App.$anonfun$main$1$adapted(App.scala:76)
at scala.collection.immutable.List.foreach(List.scala:389)
at scala.App.main(App.scala:76)
at scala.App.main$(App.scala:74)
at barstools.tapeout.transforms.GenerateTop$.main(Generate.scala:116)
at barstools.tapeout.transforms.GenerateTop.main(Generate.scala)
Caused by: java.util.NoSuchElementException: key not found: ExampleTop
at scala.collection.MapLike.default(MapLike.scala:232)
at scala.collection.MapLike.default$(MapLike.scala:231)
at scala.collection.AbstractMap.default(Map.scala:59)
at scala.collection.MapLike.apply(MapLike.scala:141)
at scala.collection.MapLike.apply$(MapLike.scala:140)
at scala.collection.AbstractMap.apply(Map.scala:59)
at barstools.tapeout.transforms.RemoveUnusedModules.execute(RemoveUnusedModules.scala:46)
at firrtl.Transform.$anonfun$runTransform$2(Compiler.scala:199)
at firrtl.Utils$.time(Utils.scala:186)
at firrtl.Transform.runTransform(Compiler.scala:199)
at firrtl.Compiler.$anonfun$compile$2(Compiler.scala:443)
at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:122)
at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:118)
at scala.collection.immutable.List.foldLeft(List.scala:86)
at firrtl.Compiler.$anonfun$compile$1(Compiler.scala:443)
at firrtl.Utils$.time(Utils.scala:186)
at firrtl.Compiler.compile(Compiler.scala:443)
at firrtl.Compiler.compile$(Compiler.scala:439)
at firrtl.VerilogCompiler.compile(LoweringCompilers.scala:162)
at firrtl.Driver$.$anonfun$execute$1(Driver.scala:242)
... 18 more
/mnt/e/Project/project-template/Makefrag:65: recipe for target '/mnt/e/Project/project-template/verisim/generated-src/example.TestHarness.PWMConfig.top.v' failed
make: *** [/mnt/e/Project/project-template/verisim/generated-src/example.TestHarness.PWMConfig.top.v] Error 1

Hi, guys,

I am new about chisel and rocket project so I am trying learn things about them by following this project-template.
I can successfully run this project using DefaultExampleConfig and SimBlockDeviceConfig, but when I tried the PWMConfig, I failed in the make CONFIG=PWMConfig command.

The error is as the following:

Could you please tell me how to fix this problem and what's cause?
Any advice will be helpful! Thanks a lot!

info] Running example.Generator /home/dd/devlop/riscv/chisel/project-template/project-template/verisim/generated-src example TestHarness example PWMConfig
[info] [0.012] Elaborating design...
Interrupt map (2 harts 0 interrupts):

[error] (run-main-0) java.lang.reflect.InvocationTargetException
java.lang.reflect.InvocationTargetException
        at sun.reflect.NativeConstructorAccessorImpl.newInstance0(Native Method)
        at sun.reflect.NativeConstructorAccessorImpl.newInstance(NativeConstructorAccessorImpl.java:62)
        at sun.reflect.DelegatingConstructorAccessorImpl.newInstance(DelegatingConstructorAccessorImpl.java:45)
        at java.lang.reflect.Constructor.newInstance(Constructor.java:423)
        at testchipip.GeneratorApp$$anonfun$circuit$1.apply(Generator.scala:22)
        at testchipip.GeneratorApp$$anonfun$circuit$1.apply(Generator.scala:19)
        at chisel3.core.Module$.do_apply(Module.scala:42)
        at chisel3.Driver$$anonfun$elaborate$1.apply(Driver.scala:92)
        at chisel3.Driver$$anonfun$elaborate$1.apply(Driver.scala:92)
        at chisel3.internal.Builder$$anonfun$build$1.apply(Builder.scala:240)
        at chisel3.internal.Builder$$anonfun$build$1.apply(Builder.scala:238)
        at scala.util.DynamicVariable.withValue(DynamicVariable.scala:58)
        at chisel3.internal.Builder$.build(Builder.scala:238)
        at chisel3.Driver$.elaborate(Driver.scala:92)
        at testchipip.GeneratorApp$class.circuit(Generator.scala:19)
        at example.Generator$.circuit$lzycompute(TestHarness.scala:20)
        at example.Generator$.circuit(TestHarness.scala:20)
        at testchipip.GeneratorApp$class.generateFirrtl(Generator.scala:30)
        at example.Generator$.generateFirrtl(TestHarness.scala:20)
        at example.Generator$.delayedEndpoint$example$Generator$1(TestHarness.scala:21)
        at example.Generator$delayedInit$body.apply(TestHarness.scala:20)
        at scala.Function0$class.apply$mcV$sp(Function0.scala:34)
        at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:12)
        at scala.App$$anonfun$main$1.apply(App.scala:76)
        at scala.App$$anonfun$main$1.apply(App.scala:76)
        at scala.collection.immutable.List.foreach(List.scala:381)
        at scala.collection.generic.TraversableForwarder$class.foreach(TraversableForwarder.scala:35)
        at scala.App$class.main(App.scala:76)
        at example.Generator$.main(TestHarness.scala:20)
        at example.Generator.main(TestHarness.scala)
        at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
        at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)
        at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
        at java.lang.reflect.Method.invoke(Method.java:498)
Caused by: java.lang.IllegalArgumentException: requirement failed
at scala.Predef$.require(Predef.scala:207)
        at example.PWMTLModule$class.$init$(PWM.scala:46)
        at example.PWMTL$$anonfun$5$$anon$1.(PWM.scala:75)
        at example.PWMTL$$anonfun$5.apply(PWM.scala:75)
        at example.PWMTL$$anonfun$5.apply(PWM.scala:75)
        at freechips.rocketchip.tilelink.TLRegisterRouter.module$lzycompute(RegisterRouter.scala:145)
        at freechips.rocketchip.tilelink.TLRegisterRouter.module(RegisterRouter.scala:145)
        at freechips.rocketchip.tilelink.TLRegisterRouter.module(RegisterRouter.scala:128)
        at freechips.rocketchip.diplomacy.LazyModule$$anonfun$instantiate$1$$anonfun$apply$5.apply(LazyModule.scala:61)
        at freechips.rocketchip.diplomacy.LazyModule$$anonfun$instantiate$1$$anonfun$apply$5.apply(LazyModule.scala:61)
        at chisel3.core.Module$.do_apply(Module.scala:42)
        at freechips.rocketchip.diplomacy.LazyModule$$anonfun$instantiate$1.apply(LazyModule.scala:61)
        at freechips.rocketchip.diplomacy.LazyModule$$anonfun$instantiate$1.apply(LazyModule.scala:58)
        at scala.collection.immutable.List.foreach(List.scala:381)
        at freechips.rocketchip.diplomacy.LazyModule.instantiate(LazyModule.scala:58)
        at freechips.rocketchip.diplomacy.LazyModuleImpLike$class.$init$(LazyModule.scala:154)
        at freechips.rocketchip.diplomacy.LazyMultiIOModuleImp.(LazyModule.scala:161)
        at freechips.rocketchip.coreplex.BareCoreplexModule.(BaseCoreplex.scala:25)
        at freechips.rocketchip.coreplex.BaseCoreplexModule.(BaseCoreplex.scala:91)
        at freechips.rocketchip.coreplex.RocketCoreplexModule.(RocketCoreplex.scala:129)
        at example.ExampleTopModule.(Top.scala:18)
        at example.ExampleTopWithPWMModule.(Top.scala:31)
        at example.ExampleTopWithPWM.module$lzycompute(Top.scala:27)
        at example.ExampleTopWithPWM.module(Top.scala:27)
        at example.WithPWM$$anonfun$$lessinit$greater$2$$anonfun$apply$2$$anonfun$applyOrElse$2$$anonfun$apply$6.apply(Configs.scala:16)
        at example.WithPWM$$anonfun$$lessinit$greater$2$$anonfun$apply$2$$anonfun$applyOrElse$2$$anonfun$apply$6.apply(Configs.scala:16)
        at chisel3.core.Module$.do_apply(Module.scala:42)
        at example.WithPWM$$anonfun$$lessinit$greater$2$$anonfun$apply$2$$anonfun$applyOrElse$2.apply(Configs.scala:16)
        at example.WithPWM$$anonfun$$lessinit$greater$2$$anonfun$apply$2$$anonfun$applyOrElse$2.apply(Configs.scala:15)
        at example.TestHarness.(TestHarness.scala:15)
        at sun.reflect.NativeConstructorAccessorImpl.newInstance0(Native Method)
        at sun.reflect.NativeConstructorAccessorImpl.newInstance(NativeConstructorAccessorImpl.java:62)
        at sun.reflect.DelegatingConstructorAccessorImpl.newInstance(DelegatingConstructorAccessorImpl.java:45)
        at java.lang.reflect.Constructor.newInstance(Constructor.java:423)
        at testchipip.GeneratorApp$$anonfun$circuit$1.apply(Generator.scala:22)
        at testchipip.GeneratorApp$$anonfun$circuit$1.apply(Generator.scala:19)
        at chisel3.core.Module$.do_apply(Module.scala:42)
        at chisel3.Driver$$anonfun$elaborate$1.apply(Driver.scala:92)
        at chisel3.Driver$$anonfun$elaborate$1.apply(Driver.scala:92)
        at chisel3.internal.Builder$$anonfun$build$1.apply(Builder.scala:240)
        at chisel3.internal.Builder$$anonfun$build$1.apply(Builder.scala:238)
        at scala.util.DynamicVariable.withValue(DynamicVariable.scala:58)
        at chisel3.internal.Builder$.build(Builder.scala:238)
        at chisel3.Driver$.elaborate(Driver.scala:92)
        at testchipip.GeneratorApp$class.circuit(Generator.scala:19)
        at example.Generator$.circuit$lzycompute(TestHarness.scala:20)
        at example.Generator$.circuit(TestHarness.scala:20)
        at testchipip.GeneratorApp$class.generateFirrtl(Generator.scala:30)
        at example.Generator$.generateFirrtl(TestHarness.scala:20)
        at example.Generator$.delayedEndpoint$example$Generator$1(TestHarness.scala:21)
        at example.Generator$delayedInit$body.apply(TestHarness.scala:20)
        at scala.Function0$class.apply$mcV$sp(Function0.scala:34)
        at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:12)
        at scala.App$$anonfun$main$1.apply(App.scala:76)
        at scala.App$$anonfun$main$1.apply(App.scala:76)
        at scala.collection.immutable.List.foreach(List.scala:381)
        at scala.collection.generic.TraversableForwarder$class.foreach(TraversableForwarder.scala:35)
        at scala.App$class.main(App.scala:76)
        at example.Generator$.main(TestHarness.scala:20)
        at example.Generator.main(TestHarness.scala)
	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
        at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)
        at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
        at java.lang.reflect.Method.invoke(Method.java:498)
[trace] Stack trace suppressed: run last compile:runMain for the full output.
java.lang.RuntimeException: Nonzero exit code: 1
        at scala.sys.package$.error(package.scala:27)
[trace] Stack trace suppressed: run last compile:runMain for the full output.
[error] (compile:runMain) Nonzero exit code: 1
[error] Total time: 6 s, completed Sep 29, 2017 2:35:45 PM

Hi,

I happened to perform make clean in my /rocket-chip/emulator in order to make new CONFIG.
But right after that, upon new make will give me make error:

make: *** No rule to make target '~/project-template/rocket-chip/emulator/generated-src/rocketchip.RoccExConfig.fir', needed by ~/project-template/rocket-chip/emulator/generated-src/rocketchip.RoccExConfig.v'. Stop.

Any advice?
Thanks

While in theory, commit on master check seems like a good idea I think it needs to be revisited. Do we want this check here to error? Or do we want it to be a warning instead? In the current case, testchipip needs to have its PR's merged for things to work. So in the meantime, the testchipip commit does not point to master. I think that this case will probably be more frequent so not erroring would be better. Thoughts?

riscv-tools no longer includes riscv-gnu-toolchain.

module PWMTL_pwm :
input clock : Clock
input reset : UInt<1>
output io : {interrupts : {}, flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<14>, mask : UInt<4>, data : UInt<32>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, address : UInt<14>, mask : UInt<4>, data : UInt<32>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<14>, data : UInt<32>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}, pwmout : UInt<1>}

clock is invalid
reset is invalid
io is invalid
reg period : UInt<32>, clock @[PWM.scala 49:19]
reg duty : UInt<32>, clock @[PWM.scala 51:17]
reg enable : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[PWM.scala 53:23]
inst base of PWMBase @[PWM.scala 55:20]  

// comments : in lines above , PWMbase shall be instanced. however, at the end , PWMBase module is totally removed, I don't know why , I just follow the instruction steps make PROJECT=example Confing= PWMConfig, nothing else. The result is PWMBase disappear

Any one who have same situations that could share ?

io.pwmout <= base.io.pwmout @[PWM.scala 56:13]

Several retreat attendees mentioned Docker images as a distribution format. I think this is a good idea.

At the very least, we should make the init scripts install all required packages that are not in a base Ubuntu install.

Currently, the CI runs off a manually uploaded docker image. We should rebuild this docker image in the CI, and deploy it as well.

• Move Dockerfile (used in CI) from riscv-boom to chipyard
• Add script(s) to install required packages in base OS(s)
• Rebuild Docker container and deploy in CI

At which address the Serial Device loads the program using TSI?
How does rocket-chip know the address to jump to after binary loading is finished?

Hello everyone,

What is the flow to do Testbench (for istance in VCS) after the generation of Verilog files in the folder "vsim" and after the synthesis in Synopsys Design Vision?

The 3 files generated are :

example.TestHarness.DefaultConfig.harness.v
example.TestHarness.DefaultConfig.mems.v
example.TestHarness.DefaultConfig.top.v

I have synthesized the "Rocket Tile" in Design Vision with the last file "top.v" and now I want to do testbench after synthesis in VCS.
I guess that the testbench file is "harness.v" but I have read that this file serves only as an HTIF interface for the testbench files like "TestDriver.v" "SimSerial.v" "AsyncResetReg.v" etc.

Is this thought right?

Then, I have generated a Rocket Config that include a Custom Accelerator.
Do I have testbench files at the end that consider my accelerator?

Thank you all

This makes it hard to diff your version of common files from rocket, coreplex, config, etc. I am unclear why this extra name specificity when I would assume you could just default this?
Also, why do you use "chip" vs. "rocketchip", and the better named "amba" vs. "uncore". I can understand that last one, but is it worth having a different name for the same files?

Hello,

i followed the tutorial and succesfully compiled the verilator emulator with the PWM.
However running the emulator with the example code always leads to a segfault.

../emulator/emulator-rocketchip-PWMTLConfig ../riscv-tools/riscv-pk/build/pk pwm
z 0000000000000000 ra 00000000000101b8 sp 000000000feeeb10 gp 0000000000011d30
tp 0000000000000000 t0 0000000000011598 t1 0000000000011598 t2 0000000000000000
s0 000000000feeeb40 s1 0000000000000000 a0 0000000000002000 a1 0000000000000014
a2 0000000000000000 a3 0000000000000000 a4 0000000000000014 a5 0000000000002000
a6 0000000000000000 a7 0000000000000000 s2 0000000000000000 s3 0000000000000000
s4 0000000000000000 s5 0000000000000000 s6 0000000000000000 s7 0000000000000000
s8 0000000000000000 s9 0000000000000000 sA 0000000000000000 sB 0000000000000000
t3 0000000000000000 t4 0000000000000000 t5 0000000000000000 t6 0000000000000000
pc 0000000000010188 va 0000000000002000 insn ffffffff sr 8000000000006000
User store segfault @ 0x0000000000002000
*** FAILED *** (code = -1, seed 1489144863) after 2329415 cycles

Is there anybody who had the same issue already and might point me in the right direction?
Any help is very appreciated.

Thanks,
Lucas

When I run make in the "verisim" directory, something goes wrong.

vicco@ubuntu:~/project-template/verisim$ make
cd /home/vicco/project-template/rocket-chip && java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar /home/vicco/project-template/rocket-chip/sbt-launch.jar pack
Java HotSpot(TM) 64-Bit Server VM warning: ignoring option MaxPermSize=256M; support was removed in 8.0
[info] Loading project definition from /home/vicco/project-template/rocket-chip/project
Using addons:
[info] Set current project to rocketchip (in build file:/home/vicco/project-template/rocket-chip/)
[info] Updating {file:/home/vicco/project-template/rocket-chip/}coreMacros...
[info] Resolving edu.berkeley.cs#firrtl_2.11;1.1-SNAPSHOT ...
[warn] module not found: edu.berkeley.cs#firrtl_2.11;1.1-SNAPSHOT
[warn] ==== local: tried
[warn] /home/vicco/.ivy2/local/edu.berkeley.cs/firrtl_2.11/1.1-SNAPSHOT/ivys/ivy.xml
[warn] ==== public: tried
[warn] https://repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.11/1.1-SNAPSHOT/firrtl_2.11-1.1-SNAPSHOT.pom
[info] Resolving jline#jline;2.12.1 ...
[warn] ::::::::::::::::::::::::::::::::::::::::::::::
[warn] :: UNRESOLVED DEPENDENCIES ::
[warn] ::::::::::::::::::::::::::::::::::::::::::::::
[warn] :: edu.berkeley.cs#firrtl_2.11;1.1-SNAPSHOT: not found
[warn] ::::::::::::::::::::::::::::::::::::::::::::::
[warn]
[warn] Note: Unresolved dependencies path:
[warn] edu.berkeley.cs:firrtl_2.11:1.1-SNAPSHOT
[warn] +- edu.berkeley.cs:coremacros_2.11:3.1-SNAPSHOT
sbt.ResolveException: unresolved dependency: edu.berkeley.cs#firrtl_2.11;1.1-SNAPSHOT: not found
at sbt.IvyActions$.sbt$IvyActions$$resolve(IvyActions.scala:313)
at sbt.IvyActions$$anonfun$updateEither$1.apply(IvyActions.scala:191)
at sbt.IvyActions$$anonfun$updateEither$1.apply(IvyActions.scala:168)
at sbt.IvySbt$Module$$anonfun$withModule$1.apply(Ivy.scala:156)
at sbt.IvySbt$Module$$anonfun$withModule$1.apply(Ivy.scala:156)
at sbt.IvySbt$$anonfun$withIvy$1.apply(Ivy.scala:133)
at sbt.IvySbt.sbt$IvySbt$$action$1(Ivy.scala:57)
at sbt.IvySbt$$anon$4.call(Ivy.scala:65)
at xsbt.boot.Locks$GlobalLock.withChannel$1(Locks.scala:93)
at xsbt.boot.Locks$GlobalLock.xsbt$boot$Locks$GlobalLock$$withChannelRetries$1(Locks.scala:78)
at xsbt.boot.Locks$GlobalLock$$anonfun$withFileLock$1.apply(Locks.scala:97)
at xsbt.boot.Using$.withResource(Using.scala:10)
at xsbt.boot.Using$.apply(Using.scala:9)
at xsbt.boot.Locks$GlobalLock.ignoringDeadlockAvoided(Locks.scala:58)
[error] (coreMacros/*:update) sbt.ResolveException: unresolved dependency: edu.berkeley.cs#firrtl_2.11;1.1-SNAPSHOT: not found
[error] Total time: 5 s, completed Apr 5, 2017 11:01:15 PM
/home/vicco/project-template/Makefrag:15: recipe for target '/home/vicco/project-template/lib/rocketchip.stamp' failed
make: *** [/home/vicco/project-template/lib/rocketchip.stamp] Error 1

Currently there are 4 SBT calls whenever building RTL. Find a way to simplify the build process to build faster.

• Reduce SBT calls to 2 (1. Gen Sim Files, Normal Elaboration, 2. GenTop, Harness)
• Other?

We should have one of those

Hi,

I did a clean install as described in th README and I'm trying to build the default example by running "make" in the verisim directory.

The problem seems to be that VTestHarness.mk is used as a makefile but it's empty... (which is logic since it seems to be created by touch just before the "make" that crashes). Here's the output :

touch riscv/project-template/verisim/generated-src/example.TestHarness.DefaultExampleConfig/VTestHarness.mk
make VM_PARALLEL_BUILDS=1 -C riscv/project-template/verisim/generated-src/example.TestHarness.DefaultExampleConfig -f VTestHarness.mk
make[1]: Entering directory 'riscv/project-template/verisim/generated-src/example.TestHarness.DefaultExampleConfig'
make[1]: *** No targets. Stop.
make[1]: Leaving directory '/riscv/project-template/verisim/generated-src/example.TestHarness.DefaultExampleConfig'
Makefile:55: recipe for target '/riscv/project-template/verisim/simulator-example-DefaultExampleConfig' failed
make: *** [/riscv/project-template/verisim/simulator-example-DefaultExampleConfig] Error 2

Do you have any idea what would be the problem?

Thanks!

I have 3 questions about PWMTL. I'm new to this project so the questions may looks amateure but I really need your help. Thanks!

After
cd verisim
make PROJECT=pwm CONFIG=PWMTLConfig
I saw
pwm {
addr 0x2000;
size 0x1000;
}
on the screen.
But when I look in PWM.scala,Top.scala,TestHarness.scala,Configs.scala, I couldn't find out how to change these parameters. So what should I do if I want to change them?

Besides, in pwm.c, it define 3 registers
#define PWM_PERIOD 0x2000
#define PWM_DUTY 0x2008
#define PWM_ENABLE 0x2010
According to PWM.scala, the reg address can be distinguish by the lower 2bits of full_addr, but I'm still not sure what does the full_addr look like.Because the 3 regs are all end with 00, so how can we distinguish them by the lower 2bits?Or in another words, why the address of Reg PWM_DUTY is 0x2008?If I change it to 0x2018 and write something into this address, what should I do to make sure PWM find the right address and update the the register?

Last question, can we make sure the PWM is working well? In pwm.c we only write some data in the regs and enable the PWM, but I don't know if the module really works.

Similar to how generated-srcs has the sources for each config split into a separate folders with the name of the config/system, do something similar with run-asm-tests and when generating things like the .vpd.

We should have a CI rule to check that the submodule commits this repository references exist on the master branches of their respective repositories.

Hello @mwachs5 ,

I'm working with a Zedboard in /fpga-zynq/zedboard and I want to run a LED blinking program.

Could you please provide any pointers on how to use GPIO instead of PWM in the Adding an MMIO peripheral section ?

I'm a beginner so any help would be appreciated.

Thank you

Hi!

I tried to add some memory-mapped registers in PWMTLModule:

regmap(
0x00 -> Seq(
RegField(32, zxheroperiod)),
0x04 -> Seq(
RegField(32, duty)),
0x08 -> Seq(
RegField(1, enable)),
0x09 -> Seq(
RegField(32, out)),
0x0d -> Seq(
RegField(32, addr1)
),
0x11 -> Seq(
RegField(32, waddr1)))

But I got errors when I ran make CONFIG=PWMConfig:

: Warning (simple_bus_reg): Node /soc/external-interrupts missing or empty reg/ranges property
[error] (run-main-0) java.lang.reflect.InvocationTargetException
[error] java.lang.reflect.InvocationTargetException
[error] at sun.reflect.NativeConstructorAccessorImpl.newInstance0(Native Method)
[error] at sun.reflect.NativeConstructorAccessorImpl.newInstance(NativeConstructorAccessorImpl.java:62)
[error] at sun.reflect.DelegatingConstructorAccessorImpl.newInstance(DelegatingConstructorAccessorImpl.java:45)
[error] at java.lang.reflect.Constructor.newInstance(Constructor.java:423)
[error] at testchipip.GeneratorApp$$anonfun$circuit$1.apply(Generator.scala:22)
[error] at testchipip.GeneratorApp$$anonfun$circuit$1.apply(Generator.scala:19)
[error] at chisel3.core.Module$.do_apply(Module.scala:49)
[error] at chisel3.Driver$$anonfun$elaborate$1.apply(Driver.scala:93)
[error] at chisel3.Driver$$anonfun$elaborate$1.apply(Driver.scala:93)
[error] at chisel3.internal.Builder$$anonfun$build$1.apply(Builder.scala:297)
[error] at chisel3.internal.Builder$$anonfun$build$1.apply(Builder.scala:295)
[error] at scala.util.DynamicVariable.withValue(DynamicVariable.scala:58)
[error] at chisel3.internal.Builder$.build(Builder.scala:295)
[error] at chisel3.Driver$.elaborate(Driver.scala:93)
[error] at testchipip.GeneratorApp$class.circuit(Generator.scala:19)
[error] at example.Generator$.circuit$lzycompute(TestHarness.scala:24)
[error] at example.Generator$.circuit(TestHarness.scala:24)
[error] at testchipip.GeneratorApp$class.generateFirrtl(Generator.scala:30)
[error] at example.Generator$.generateFirrtl(TestHarness.scala:24)
[error] at example.Generator$.delayedEndpoint$example$Generator$1(TestHarness.scala:25)
[error] at example.Generator$delayedInit$body.apply(TestHarness.scala:24)
[error] at scala.Function0$class.apply$mcV$sp(Function0.scala:34)
[error] at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:12)
[error] at scala.App$$anonfun$main$1.apply(App.scala:76)
[error] at scala.App$$anonfun$main$1.apply(App.scala:76)
[error] at scala.collection.immutable.List.foreach(List.scala:392)
[error] at scala.collection.generic.TraversableForwarder$class.foreach(TraversableForwarder.scala:35)
[error] at scala.App$class.main(App.scala:76)
[error] at example.Generator$.main(TestHarness.scala:24)
[error] at example.Generator.main(TestHarness.scala)
[error] at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
[error] at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)
[error] at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
[error] at java.lang.reflect.Method.invoke(Method.java:498)
[error] at sbt.Run.invokeMain(Run.scala:93)
[error] at sbt.Run.run0(Run.scala:87)
[error] at sbt.Run.execute$1(Run.scala:65)
[error] at sbt.Run.$anonfun$run$4(Run.scala:77)
[error] at scala.runtime.java8.JFunction0$mcV$sp.apply(JFunction0$mcV$sp.java:12)
[error] at sbt.util.InterfaceUtil$$anon$1.get(InterfaceUtil.scala:10)
[error] at sbt.TrapExit$App.run(TrapExit.scala:252)
[error] at java.lang.Thread.run(Thread.java:748)
[error] Caused by: java.lang.IllegalArgumentException: requirement failed: Field at word 1*(8B) has bits [40, 72), which exceeds word limit.
[error] at scala.Predef$.require(Predef.scala:224)
[error] at freechips.rocketchip.regmapper.RegMapper$$anonfun$10$$anonfun$apply$8.apply(RegMapper.scala:103)
[error] at freechips.rocketchip.regmapper.RegMapper$$anonfun$10$$anonfun$apply$8.apply(RegMapper.scala:100)
[error] at scala.collection.immutable.List.foreach(List.scala:392)
[error] at freechips.rocketchip.regmapper.RegMapper$$anonfun$10.apply(RegMapper.scala:100)
[error] at freechips.rocketchip.regmapper.RegMapper$$anonfun$10.apply(RegMapper.scala:92)
[error] at scala.collection.immutable.List.map(List.scala:288)
[error] at freechips.rocketchip.regmapper.RegMapper$.apply(RegMapper.scala:92)
[error] at freechips.rocketchip.tilelink.TLRegisterNode.regmap(RegisterRouter.scala:62)
[error] at freechips.rocketchip.tilelink.TLRegModule.regmap(RegisterRouter.scala:122)
[error] at example.PWMTLModule$class.$init$(PWM.scala:95)
[error] at example.PWMTL$$anonfun$9$$anon$2.(PWM.scala:129)
[error] at example.PWMTL$$anonfun$9.apply(PWM.scala:129)
[error] at example.PWMTL$$anonfun$9.apply(PWM.scala:129)
[error] at freechips.rocketchip.tilelink.TLRegisterRouter.module$lzycompute(RegisterRouter.scala:142)
[error] at freechips.rocketchip.tilelink.TLRegisterRouter.module(RegisterRouter.scala:142)
[error] at freechips.rocketchip.tilelink.TLRegisterRouter.module(RegisterRouter.scala:125)
[error] at freechips.rocketchip.diplomacy.LazyModuleImpLike$$anonfun$4$$anonfun$5.apply(LazyModule.scala:156)
[error] at freechips.rocketchip.diplomacy.LazyModuleImpLike$$anonfun$4$$anonfun$5.apply(LazyModule.scala:156)
[error] at chisel3.core.Module$.do_apply(Module.scala:49)
[error] at freechips.rocketchip.diplomacy.LazyModuleImpLike$$anonfun$4.apply(LazyModule.scala:156)
[error] at freechips.rocketchip.diplomacy.LazyModuleImpLike$$anonfun$4.apply(LazyModule.scala:154)
[error] at scala.collection.immutable.List.flatMap(List.scala:338)
[error] at freechips.rocketchip.diplomacy.LazyModuleImpLike$class.instantiate(LazyModule.scala:154)
[error] at freechips.rocketchip.diplomacy.LazyModuleImp.instantiate(LazyModule.scala:183)
[error] at freechips.rocketchip.diplomacy.LazyModuleImp.(LazyModule.scala:184)
[error] at freechips.rocketchip.subsystem.BareSubsystemModuleImp.(BaseSubsystem.scala:19)
[error] at freechips.rocketchip.subsystem.BaseSubsystemModuleImp.(BaseSubsystem.scala:101)
[error] at freechips.rocketchip.subsystem.RocketSubsystemModuleImp.(RocketSubsystem.scala:154)
[error] at example.ExampleTopModule.(Top.scala:20)
[error] at example.ExampleTopWithPWMModule.(Top.scala:35)
[error] at example.ExampleTopWithPWM.module$lzycompute(Top.scala:31)
[error] at example.ExampleTopWithPWM.module(Top.scala:31)
[error] at example.WithPWM$$anonfun$$lessinit$greater$3$$anonfun$apply$3$$anonfun$applyOrElse$2$$anonfun$apply$7.apply(Configs.scala:29)
[error] at example.WithPWM$$anonfun$$lessinit$greater$3$$anonfun$apply$3$$anonfun$applyOrElse$2$$anonfun$apply$7.apply(Configs.scala:29)
[error] at chisel3.core.Module$.do_apply(Module.scala:49)
[error] at example.WithPWM$$anonfun$$lessinit$greater$3$$anonfun$apply$3$$anonfun$applyOrElse$2.apply(Configs.scala:29)
[error] at example.WithPWM$$anonfun$$lessinit$greater$3$$anonfun$apply$3$$anonfun$applyOrElse$2.apply(Configs.scala:28)
[error] at example.TestHarness.(TestHarness.scala:15)
[error] at sun.reflect.NativeConstructorAccessorImpl.newInstance0(Native Method)
[error] at sun.reflect.NativeConstructorAccessorImpl.newInstance(NativeConstructorAccessorImpl.java:62)
[error] at sun.reflect.DelegatingConstructorAccessorImpl.newInstance(DelegatingConstructorAccessorImpl.java:45)
[error] at java.lang.reflect.Constructor.newInstance(Constructor.java:423)
[error] at testchipip.GeneratorApp$$anonfun$circuit$1.apply(Generator.scala:22)
[error] at testchipip.GeneratorApp$$anonfun$circuit$1.apply(Generator.scala:19)
[error] at chisel3.core.Module$.do_apply(Module.scala:49)
[error] at chisel3.Driver$$anonfun$elaborate$1.apply(Driver.scala:93)
[error] at chisel3.Driver$$anonfun$elaborate$1.apply(Driver.scala:93)
[error] at chisel3.internal.Builder$$anonfun$build$1.apply(Builder.scala:297)
[error] at chisel3.internal.Builder$$anonfun$build$1.apply(Builder.scala:295)
[error] at scala.util.DynamicVariable.withValue(DynamicVariable.scala:58)
[error] at chisel3.internal.Builder$.build(Builder.scala:295)
[error] at chisel3.Driver$.elaborate(Driver.scala:93)
[error] at testchipip.GeneratorApp$class.circuit(Generator.scala:19)
[error] at example.Generator$.circuit$lzycompute(TestHarness.scala:24)
[error] at example.Generator$.circuit(TestHarness.scala:24)
[error] at testchipip.GeneratorApp$class.generateFirrtl(Generator.scala:30)
[error] at example.Generator$.generateFirrtl(TestHarness.scala:24)
[error] at example.Generator$.delayedEndpoint$example$Generator$1(TestHarness.scala:25)
[error] at example.Generator$delayedInit$body.apply(TestHarness.scala:24)
[error] at scala.Function0$class.apply$mcV$sp(Function0.scala:34)
[error] at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:12)
[error] at scala.App$$anonfun$main$1.apply(App.scala:76)
[error] at scala.App$$anonfun$main$1.apply(App.scala:76)
[error] at scala.collection.immutable.List.foreach(List.scala:392)
[error] at scala.collection.generic.TraversableForwarder$class.foreach(TraversableForwarder.scala:35)
[error] at scala.App$class.main(App.scala:76)
[error] at example.Generator$.main(TestHarness.scala:24)
[error] at example.Generator.main(TestHarness.scala)
[error] at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
[error] at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)
[error] at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
[error] at java.lang.reflect.Method.invoke(Method.java:498)
[error] at sbt.Run.invokeMain(Run.scala:93)
[error] at sbt.Run.run0(Run.scala:87)
[error] at sbt.Run.execute$1(Run.scala:65)
[error] at sbt.Run.$anonfun$run$4(Run.scala:77)
[error] at scala.runtime.java8.JFunction0$mcV$sp.apply(JFunction0$mcV$sp.java:12)
[error] at sbt.util.InterfaceUtil$$anon$1.get(InterfaceUtil.scala:10)
[error] at sbt.TrapExit$App.run(TrapExit.scala:252)
[error] at java.lang.Thread.run(Thread.java:748)
[error] java.lang.RuntimeException: Nonzero exit code: 1
[error] at sbt.Run$.executeTrapExit(Run.scala:124)
[error] at sbt.Run.run(Run.scala:77)
[error] at sbt.Defaults$.$anonfun$bgRunMainTask$6(Defaults.scala:1147)
[error] at sbt.Defaults$.$anonfun$bgRunMainTask$6$adapted(Defaults.scala:1142)
[error] at sbt.internal.BackgroundThreadPool.$anonfun$run$1(DefaultBackgroundJobService.scala:366)
[error] at scala.runtime.java8.JFunction0$mcV$sp.apply(JFunction0$mcV$sp.java:12)
[error] at scala.util.Try$.apply(Try.scala:209)
[error] at sbt.internal.BackgroundThreadPool$BackgroundRunnable.run(DefaultBackgroundJobService.scala:289)
[error] at java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1149)
[error] at java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:624)
[error] at java.lang.Thread.run(Thread.java:748)
[error] (Compile / runMain) Nonzero exit code: 1
[error] Total time: 16 s, completed Jan 23, 2019 5:47:12 PM

I am confused why I got these errors. I found code in BlockDevices.scala:

regmap(
0x00 -> Seq(RegField(pAddrBits, addr)),
0x08 -> Seq(RegField(sectorBits, offset)),
0x0C -> Seq(RegField(sectorBits, len)),
0x10 -> Seq(RegField(1, write)),
0x11 -> Seq(RegField.r(tagBits, allocRead)),
0x12 -> Seq(RegField.r(backendQueueCountBits, io.back.nallocate)),
0x13 -> Seq(RegField.r(tagBits, io.back.complete)),
0x14 -> Seq(RegField.r(backendQueueCountBits, io.back.ncomplete)),
0x18 -> Seq(RegField.r(sectorBits, io.info.nsectors)),
0x1C -> Seq(RegField.r(sectorBits, io.info.max_req_len)))

I can run make CONFIG=SimBlockDeviceConfig without errors. Does anyone know what's wrong with my code?

Thanks a lot!

I follow the tutorial and run pwm.riscv successfully, now I wonder how to know how many cycles the program takes?
To go further, can I know how many cycles each function takes?
for example,If I write a sort.c to run on ./simulator-myproject-myConfig, and sort.c contains DataPrepare(),Sort() and DataCompare() 3 functions in main(), can I get the cycles cost for each function?

Thanks for your help.

The currently pinned version of the testchip-ip repository does not contain the verilator-harness.cc mentioned in the verisim Makefile. It was deleted here.

https://github.com/ucb-bar/project-template/blob/048492e54cecf76860c4c299e81f66be64873fa3/verisim/Makefile#L34

The current version needs a rocket-chip bump as testchip's csrc/SimSerial.cc appears to be ahead of rocket-chip's riscv-tools/riscv-fesvr. See:

project-template/testchipip/csrc/SimSerial.cc:29:10: error: ‘class tsi_t’ has no member named ‘tick’
     tsi->tick(out_valid, out_bits, in_ready);

Confirm that cmd line mixins work in the current system for DSE explanation.

aka:

make CONFIG=SmallXConfig_WithSomething_WithSomething2

With the rename, we need to remove references to project-template in favor of the new name. (Rebar?).

Fetch Monitor trips with current RC bump: https://circleci.com/gh/ucb-bar/chipyard/1649?utm_campaign=vcs-integration-link&utm_medium=referral&utm_source=github-build-link

Since the longnames are incorporated into the path to simulation output now, this causes some runs to fail.

Should be fixed with chipsalliance/rocket-chip#1988

Hi,
I set XLEN=32 for whole system, so I intend to run 32 bit ELF on that system.
I just modify Makefile(in project-template/tests/)configuration to generate 32 bit ELF file.

revision part:
GCC=riscv32-unknown-elf-gcc
OBJDUMP=riscv32-unknown-elf-objdump

I only revise two statements shown above, and remain part still as original version.
However, I get errors when I utilize new Makefile.
error message:
riscv32-unknown-elf-gcc -T link.ld -static -nostdlib -nostartfiles -lgcc pwm.o crt.o syscalls.o -o pwm.riscv
syscalls.o: In function .L48': syscalls.c:(.text+0x13c): undefined reference to __umoddi3'
syscalls.o: In function .L59': syscalls.c:(.text+0x168): undefined reference to __udivdi3'
syscalls.c:(.text+0x180): undefined reference to `__umoddi3'
collect2: error: ld returned 1 exit status
make: *** [pwm.riscv] Error 1

It fails in linking stage. Obviously, it seems there are some program in systemcall.c with 32bit configuration.
Can anyone tell me how to fix it for compiling successfully?

Currently, run-asm-tests and run-bmark-tests run on hartId == 0 of the system. This is supported for when either BOOM or Rocket is hartId == 0. However, we may want to think of a way to have asm/bmark tests that can target other hartIds (and maybe incorporate this in the run make functionality. This also applies to systems where there are different cores/accelerators ... BOOM + Rocket + Hwacha + Other.

Hello,

I have referenced issue #7.
(1). I use the method RISC-V "rdcycle" instruction to measure how many cycles the program takes.
And it gets:

(2). I have also checked out with .vcd file and make sure above method get correct result.
It complete in 86975(ns), and the clock period is 2(ns).
Therefor, the program takes about 43487 cycles to complete.
image

Why the results differ dramatically? Or there is something I misunderstand?

after this commit git submodule update --init --recursive fails for me with the next error

^^/R/project-template >>> git submodule update --init --recursive
error: Server does not allow request for unadvertised object 7d3c333765920ef9175c3d0eee6a6326f5e09a18
Fetched in submodule path 'barstools', but it did not contain 7d3c333765920ef9175c3d0eee6a6326f5e09a18. Direct fetching of that commit failed.

Is this a bug that I see the VTestHarness.mk is created by touch command. And when execute make command , it returns no target to make because the VTestHarness.mk is empty. Could anyone help me please?

Currently, CI only supports builds that are under 2GBs. This is an issue when building bigger configs such as BOOM or Hwacha. Is there a way to go around this properly rather than trying to create a smaller config (in Hwacha's case this is hard since a minified Rocket core with Hwacha still needs more that 2GB to verilate)?

Thanks for the detailed MMIO device example, it's very very very helpful.
Now I wonder If there are also detailed example projects for Rocc and DMA ?

For example, I tried to follow the guidance and add a DMA port instead of MMIO, but I
don't know how to make ExtBundle work and how to test it. Thanks for your help!

https://github.com/ucb-bar/project-template/blob/d48587b6714bbc128566a5d0fac68496d732aa7c/Makefrag#L33

The generator only takes 5 args, and $(CHISEL_ARGS) seems a redundant args?
Any idea?

I rebuild the emulator with some revisions. I rebuild the project again without typing "make clean" before.
It takes about first time.
I use make -d to observe the hanging point that costs lots of time at rebuild.

hanging point:

The prerequisites of 'default' are being made.
Live child 0xaddc20 (VTestHarness.o) PID 31961

It seems it recompile to generate out VTestHarness.o(I am not sure) .
I cannot figure out why? Could anyone tells me the reasons?

Hi,
I use the following commands to build the emulator.
cd verisim
make CONFIG=PWMConfig

However, it cannot build successfully with errors.

error message:

make VM_PARALLEL_BUILDS=1 -C /users/student/project-template/verisim/generated-src/example.TestHarness.PWMConfig -f VTestHarness.mk
make[1]: Entering directory `/users/student/project-template/verisim/generated-src/example.TestHarness.PWMConfig'
g++ -I. -MMD -I/users/student/project-template/verisim/verilator/install/share/verilator/include -I/users/student/project-template/verisim/verilator/install/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -Wno-char-subscripts -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -O1 -std=c++11 -I/include -D__STDC_FORMAT_MACROS -DVERILATOR -include /users/student/project-template/rocket-chip/csrc/verilator.h -I/users/student/project-template/verisim/generated-src -include /users/student/project-template/verisim/generated-src/example.TestHarness.PWMConfig/VTestHarness.h -c -o SimSerial.o /users/student/project-template/testchipip/csrc/SimSerial.cc
/users/student/project-template/testchipip/csrc/SimSerial.cc:5:23: fatal error: fesvr/tsi.h: No such file or directory
#include <fesvr/tsi.h>

The error message reveal the program in project-template/testchipip/csrc/SimSerial.cc includes not existence file. With the clue, I go to project-template/rocket-chip/riscv-tools/riscv-fesvr/fesvr/ to check dose it exist(filet si.h). After checking, I get the conclusion that the file exists. Therefore, I have no idea with such errors.

I leverage testchipip @ 3fe8806 branch.

Can anyone tell me how to fix it for compiling successfully?

Hello,

I'm compiling the pwm.c program using riscv64-unknown-elf-gcc -o pwm pwm.c and then pk pwm. But it's not working. Should I use LLVM instead ? With clang -target riscv64 -mriscv=RV64IAMFD -S pwm.c -o pwm.S and riscv64-unknown-elf-gcc -o pwm.riscv pwm.S ?

Is it possible to use pk at all ?

make pwm gives the following:

cc -mcmodel=medany -std=gnu99 -O2 -fno-common -fno-builtin-printf -Wall  -static -nostdlib -nostartfiles -lgcc  pwm.c   -o pwm
cc: error: unrecognized argument in option ‘-mcmodel=medany’
cc: note: valid arguments to ‘-mcmodel=’ are: 32 kernel large medium small
make: *** [pwm] Error 1

Thank you

Can we also add a config that sets parameters in the L2 config?
Rocket4BankL2 or Rocket1MBL2 and just have them build in CI?
I think its important to test the number of banks and the number of memory channels. Having both of those parameters set has caused problems in the past and I think was the reason for Howie's rocket-chip PR.

Originally posted by @colinschmidt in https://github.com/ucb-bar/chipyard/pull/128/files