tymcauley Goto Github PK

arbitrary-int

A modern and lightweight implementation of arbitrary integers for Rust

barstools

Useful utilities for BAR projects

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

chisel

Chisel 3: A Modern Hardware Design Language

circt

Circuit IR Compilers and Tools

constellation

A Chisel RTL generator for network-on-chip interconnects

diplomacy

dotfiles

My collection of configuration files

dsptools

A Library of Chisel3 Tools for Digital Signal Processing

fern

Simple, efficient logging for Rust

fftgenerator

firrtl-spec

The specification for the FIRRTL language

fixedpoint

Chisel Fixed-Point Arithmetic Library

llvm-vim-syntax

vim language files for LLVM filetypes

null-ls.nvim

Use Neovim as a language server to inject LSP diagnostics, code actions, and more via Lua.

nvdla-sw

NVDLA SW adjusted for FireSim Linux Simulations

nvdla-workload

Base NVDLA Workload for FireMarshal

nvdla-wrapper

Wraps the NVDLA project for Chipyard integration

nvim-web-devicons

lua `fork` of vim-web-devicons for neovim

prezto

The configuration framework for Zsh

riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

riscv-isa-manual

RISC-V Instruction Set Manual

rocket-chip

Rocket Chip Generator

rocket-chip-blocks

RTL blocks compatible with the Rocket Chip Generator

rocket-chip-inclusive-cache

An RTL generator for a last-level shared inclusive TileLink cache controller

rocket-dsp-utils

Tools for integrating DspTools components into a rocket-chip

spike-dasm-rs

Rust implementation of spike's RISC-V disassembler, spike-dasm

testchipip

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.

xenorchestrainstallerupdater

xen-orchestra automated installer and updater