Comments (3)
Castleeee
commented on August 21, 2024
同建议中文，降低门槛，也更好向高校推广
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poemonsense
commented on August 21, 2024
从方便国内用户的角度，用中文写介绍和文档是一个好建议。我们会考虑增加中文版本
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wakafa1
commented on August 21, 2024
感谢 @ClSlaid 提供的中文 Readme，目前已经合进主线。另外即将发布的文档将会是中文版本。
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Related Issues (20)
- Incorrect Rounding Mode Handling for Specific Cases HOT 2
- Correct NEMU version for nanhu branch of XiangShan HOT 4
- Assertion failed when running EMU on nanhu-G branch HOT 8
- make emu error - Exception in thread "main" java.util.NoSuchElementException: NOOP_HOME HOT 1
- the logic of tlbBundle privilege in dmode HOT 3
- How to use profile function of verilator in XiangShan environment HOT 6
- Using XiangShan to reproduce the example code in RISC-V Architecture Programming and Practice. HOT 6
- Simulation hangs for longer running functions using the vector extension HOT 8
- How are the uncacheable and non-indempotent stores are handled? HOT 4
- How can projects using Chisel 3 and Chisel 5/6 be integrated together? HOT 1
- Is there any interface to flush L2 Cache data HOT 2
- Solution to make FIR elaboration faster
- Can not generate RTL when NUM_CORES >= 3
- 使用命令时遇到错误“已放弃（核心已转储） ” HOT 1
- Eeception while compile using "make emu EMU_THREADS=8 MFC=1 CONFIG=KunminghuV2Config" HOT 1
- Compile Exception while using "make emu EMU_THREADS=8 MFC=1 CONFIG=KunminghuV2Config", HOT 5
- Difftest failed on a RISC-V Vector memcpy workload with misaligned(in vlen granularity, not element) unit stride load HOT 1
- Assertion failed at UserYanker.scala:63 assert (!out.r.valid || r_valid) // Q must be ready faster than the response HOT 1
- make verilog NUM_CORES=4 gets error HOT 7
- In VCS simulation, multi-core simulation of some harts ended prematurely due to incorrect execution of SEQZ instruction HOT 1
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