A fast CI is what we need about xiangshan

[poemonsense]

Thanks for the feedback on CI.

Currently we are using five self-hosted servers for CI (AMD EPYC 7742). We did consider Travis-CI or other public platforms. But none of us has actually tried to do that. We are also considering migrating our repo to gitee, which uses a different CI framework. Hopefully we will build a better CI before September.

For the second question, these two EMUs are not the same. The latter one uses DRAMsim but not the former one. GitHub has a limitation on CI running time (6 hours). If we combine them into a single job, it cannot finish within 6 hours.

We are much appreciated if someone in the community could help us build the CI platform. Actually we don’t know much yet.

[ClSlaid]

Thanks for the feedback on CI.

Currently we are using five self-hosted servers for CI (AMD EPYC 7742). We did consider Travis-CI or other public platforms. But none of us has actually tried to do that. We are also considering migrating our repo to gitee, which uses a different CI framework. Hopefully we will build a better CI before September.

For the second question, these two EMUs are not the same. The latter one uses DRAMsim but not the former one. GitHub has a limitation on CI running time (6 hours). If we combine them into a single job, it cannot finish within 6 hours.

We are much appreciated if someone in the community could help us build the CI platform. Actually we don’t know much yet.

I don't know much about CI, either. After questioning my senior, who's also a chisel user, he considered your CI to be fast enough.
Maybe this is what hardware development like I think. 🤣

BTW, I've tried developing a very naive pipeline CPU in verilog last year, which did give me a bad impression about hardware development for writing annoying test benches
For example, the compiler just lets go those bad codes that will stuck the whole simulator like modelsim or vivado. Such as

// this is a test bench
always sig_trig=2'b01;
// should be "assign sig_trig=2'b1;"
// no warnings will be given out

Can Chisel avoid such a situation? Are there any recommendations on books or videos about ChiselHDL?

[AugustusWillisWang]

Information for those who are interested in enhancing XiangShan CI:

Currently, XiangShan CI does 3 jobs in parallel:

1. Generate Verilog code (not for simulation) from Chisel source code
2. Use Verilator to run simulation without DRAMsim for basic inst tests and embedded benchmarks
3. Use Verilator to run simulation with DRAMsim for spec SimPoints

Verilator simulation consists of 3 stages:

1. We need to convert Chisel to Verilog before running Verilator simulation. It can only be done with a single thread.
2. Compiling Verilator emulator. This can be done in parallel.
3. After Verilator emulator compiling, run benchmarks and inst tests. They can run in parallel.

Currently, we use a python script https://github.com/OpenXiangShan/XiangShan/blob/master/scripts/xiangshan.py to deal with environmental things.

[poemonsense]

Chisel generates synthesizable verilog. It cannot be used to write testbench.

Recommend resources: https://www.chisel-lang.org/chisel3/docs/resources/resources.html.

[xied75]

I can help on the CI front if that's needed. We can also try Azure DevOps if there is no policy against using these big clouds.