Topic: axi-stream Goto Github
Some thing interesting about axi-stream
Some thing interesting about axi-stream
axi-stream,Notes after working with Zynq platform using vivado and petalinux
User: 2uger
axi-stream,A test IP that receives a packet from the NoC, increments its the payload, and sends the packet back to the source
User: amamory
axi-stream,AXI stream protocol checking design
User: amamory
axi-stream,A one-position buffer compatible with AXI Stream interface
User: amamory
axi-stream,An IP used for testing AXI stream protocols. It uses a LFSR to generate ready and valid signals
User: amamory
axi-stream,A 2x2 mesh NoC compatible with AXI streaming interface
User: amamory
axi-stream,vivado design to test the skidbuffer IP
User: amamory
axi-stream,A demonstrator of Hermes network-on-chip communicating with the ARM processor
User: amamory
axi-stream,Zynq PS connected to a Hermes networkn-on-chip router via AXI streaming interface
User: amamory
axi-stream,A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
User: aryan-programmer
axi-stream, A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
User: aryan-programmer
axi-stream,Tutorials or projects example to use Vivado 2019.2 and Vitis
User: catarinaacsilva
axi-stream,This project is designed to delay the output of the video stream in AXI-STREAM format.
User: doudiu
axi-stream,UART to AXI Stream interface written in VHDL
User: fcayci
axi-stream,Synchronous and Asynchronous FIFO with AXI interface
User: gururavi
Home Page: https://github.com/gururavi/rtl
axi-stream,Formal verification of an ALU
User: jasnap
axi-stream,FPGA interface and driver for an OV7670 camera sensor.
User: kampi
axi-stream,An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
Organization: kastnerrg
axi-stream,Fast bwa-mem dna matching algor implemented in system verilog, fully synthesizable.
User: loykylewong
axi-stream,FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device
User: masterplayer
axi-stream,FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol
User: masterplayer
axi-stream,Performance counter to measure latency between two AXI Stream interfaces with pattern matching as trigger.
User: mnemocron
axi-stream,ASIC for executing vectorized gradient descent on linear regression problems.
User: pkill37
axi-stream,This is a collection of some examples designed in the Vivado Design Suite.
User: riyasach189
axi-stream,Various video processing projects will be shared here
User: shoukathali23
axi-stream,High throughput JPEG decoder in Verilog for FPGA
User: ultraembedded
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