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avs3-rdoq

This work presents the RTL design from our paper published in the journal TCSVT: 'Parallelized RDOQ Algorithm and Fully Pipelined Hardware Architecture for AVS3 Video Coding.'

axis-axi4-axis

This project is designed to delay the output of the video stream in AXI-STREAM format.

chaotic-carrier-wave-system-based-on-fpga

The frequency of the goal wave is dictated by the value of the logistic value in this chaotic carrier wave system, which is based on fpga design.

doudiu

hardware-implementation-of-the-canny-edge-detection-algorithm

The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.

hardware-implementation-of-the-dark-channel-prior-haze-removal-algorithm

The Dark Channel Prior technique is implemented on FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.

hardware-implementation-of-video-stitching

This open-source repository aims to stitch several separate video streams into a single video using DDR3/4 storage via the AXI interface. The interface can be easily switched to the DDR3/4 located on either the PS or PL side using HP/GP ports or MIG IP.

serial_port_router

this's a simple case of different bound rate serial port router

vehicle-license-plate-recognition-on-fpga