Topic: axi4-stream Goto Github
Some thing interesting about axi4-stream
Some thing interesting about axi4-stream
axi4-stream,A test IP that receives a packet from the NoC, increments its the payload, and sends the packet back to the source
User: amamory
axi4-stream,A 2x2 mesh NoC compatible with AXI streaming interface
User: amamory
axi4-stream,AXI4 and AXI4-Lite interface definitions
User: mmxsrup
axi4-stream,Convert data signal to axi4-stream signal
User: mmxsrup
axi4-stream,AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
Organization: osvvm
axi4-stream,A real-time audio visualizer on an FPGA. Receives and transmits audio packets via I2S, and displays the time-domain waveform of the input signal using VGA. Supports changing waveform and background colours via UART.
User: reezanvisram
axi4-stream,A collection of formal properties for hardware buses, and cores using them.
User: rlee287
axi4-stream,Lightweight AXI-Stream debugging probe
User: stevenbell
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