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License: Other
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
License: Other
Describe the bug
it stops at here
To Reproduce
Steps to reproduce the behavior:
source /home/esp/socs/xilinx-vc707-xc7vx485t/vivado/.Xil/Vivado-25650-acs30/webtalk/labtool_webtalk.tcl -notrace
INFO: [Common 17-186] '/home/esp/socs/xilinx-vc707-xc7vx485t/vivado/.Xil/Vivado-25650-acs30/webtalk/usage_statistics_ext_labtool.xml' has been successfully sent to Xilinx on Fri Jul 24 02:11:00 2020. For additional details about this file, please refer to the WebTalk help file at /home/tools/Xilinx/Vivado/2019.2/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Fri Jul 24 02:11:00 2020...
INFO Waiting for DDR calibration...
OBJCP ram.srec
OBJCP systest.bin
ESPLink address 192.168.1.7:46390
Expected behavior
i want to boot linux
Screenshots
The APB to AXI-Lite adapter apb2axil.sv
needs the following fixes:
Describe the bug
Xilinx Vivado cannot close timing on the last-level cache (LLC) for the VCU118 target FPGA board, even though Stratus HLS successfully generates the RTL of the LLC.
To Reproduce
Synthesize a basic ESP instance with the caches for the VCU118 target FPGA board.
The initial integration of Ariane did not support distributed interrupts. Therefore, the ESP device driver is currently polling the accelerator's status register to check for completion.
Now that distributed interrupts are supported, we can switch to using interrupts for ESP accelerators.
This update should be applied to /soft/ariane/drivers/esp/esp.c
Describe the bug
The script init_accelerator.sh
is not compatible with Red Hat Linux
See for example:
https://github.com/sld-columbia/esp/blob/master/utils/scripts/init_accelerator.sh#L305-L311
We should add a test to catch rhel
, for example:
if cat /etc/os-release | grep -q -i rhel; then
rename accelerator $LOWER *
fi
and add a default that terminates the script when an unknown OS is detected.
Describe the bug
In ESP we let accelerators share the same interrupt line. This works fine on Leon3, because if multiple accelerators activate the interrupt at the same time, the interrupt controller queues both requests on the same line.
It appears, however, that the RISC-V PLIC, instead, clears all requests when the first interrupt handler runs.
To Reproduce
Invoke at least two independent accelerators, using the multi-threaded ESP accelerator API: esp_run(config). Multiple executions might be required to reproduce the issue.
Expected behavior
All interrupts should be caught and handled, even when running the application several times.
To fix, we must have 'socmap' assign different interrupt lines to each accelerator when RISC-V Ariane is selected.
Describe the bug
With a fresh start from Ubuntu 18.04, an user needs
sudo apt install -y flex
to compile the RISCV toolchain.
Leon3 supports whole-cache-flush instructions according to section 86.3.11 in GrLib IP manual https://www.gaisler.com/products/grlib/grip.pdf How does ESP handle this "flush" CPU request?
cpu_msg is obtained from concatenating two fields, hwrite and hmastlock, of the ahb_slv_in_type data structure https://github.com/sld-columbia/esp/blob/master/rtl/src/sld/caches/l2_wrapper.vhd#L741, which maps to four kinds of requests (atomic R/atomic W/R/W). I think this implies that ESP L2 (and LLC of course) is never aware of the CPU's cache-flush instructions.
This mysterious comment line here https://github.com/sld-columbia/esp/blob/master/systemc/common/caches/cache_types.hpp#L64 indicates that you at least attempted to handle that request but then decided not to support it. Is that true? Why or why not? How exactly is the flush request passed down to the rest of the cache-hierarchy from L1?
Describe the bug
You can run the ESP flow on Red Hat 7.8. Add the following command to the Centos 7 instructions.
sudo yum install http://mirror.centos.org/centos/7/extras/x86_64/Packages/dtc-1.4.6-1.el7.x86_64.rpm
I couldn't find a native package for DTC, so I opted for the rpm package on the Centos 7 repository.
After pulling the most recent commit 794a0a9 from master to a local clean install of ESP, Vivado synthesis pipeline errors out with
ERROR: [Synth 8-1031] cache_attribute_array is not declared [/projects/esp/socs/xilinx-vc707-xc7vx485t/socmap.vhd:290]
ERROR: [Synth 8-1031] dma_attribute_array is not declared [/projects/esp/socs/xilinx-vc707-xc7vx485t/socmap.vhd:349]
ERROR: [Synth 8-1031] cache_tile_id is not declared [/projects/esp/socs/xilinx-vc707-xc7vx485t/socmap.vhd:463]
ERROR: [Synth 8-1031] cache_tile_id is not declared [/projects/esp/socs/xilinx-vc707-xc7vx485t/socmap.vhd:464]
ERROR: [Synth 8-1031] cache_tile_id is not declared [/projects/esp/socs/xilinx-vc707-xc7vx485t/socmap.vhd:465]
ERROR: [Synth 8-1031] cache_tile_id is not declared [/projects/esp/socs/xilinx-vc707-xc7vx485t/socmap.vhd:466]
ERROR: [Synth 8-1031] cache_tile_id is not declared [/projects/esp/socs/xilinx-vc707-xc7vx485t/socmap.vhd:467]
ERROR: [Synth 8-1031] cache_tile_id is not declared [/projects/esp/socs/xilinx-vc707-xc7vx485t/socmap.vhd:468]
ERROR: [Synth 8-1031] cache_tile_id is not declared [/projects/esp/socs/xilinx-vc707-xc7vx485t/socmap.vhd:469]
ERROR: [Synth 8-1031] cache_tile_id is not declared [/projects/esp/socs/xilinx-vc707-xc7vx485t/socmap.vhd:470]
ERROR: [Synth 8-1031] cache_tile_id is not declared [/projects/esp/socs/xilinx-vc707-xc7vx485t/socmap.vhd:471]
ERROR: [Synth 8-1031] cache_tile_id is not declared [/projects/esp/socs/xilinx-vc707-xc7vx485t/socmap.vhd:472]
ERROR: [Synth 8-1031] cache_tile_id is not declared [/projects/esp/socs/xilinx-vc707-xc7vx485t/socmap.vhd:473]
ERROR: [Synth 8-1031] cache_tile_id is not declared [/projects/esp/socs/xilinx-vc707-xc7vx485t/socmap.vhd:474]
ERROR: [Synth 8-1031] cache_tile_id is not declared [/projects/esp/socs/xilinx-vc707-xc7vx485t/socmap.vhd:475]
ERROR: [Synth 8-1031] cache_tile_id is not declared [/projects/esp/socs/xilinx-vc707-xc7vx485t/socmap.vhd:476]
ERROR: [Synth 8-1031] cache_tile_id is not declared [/projects/esp/socs/xilinx-vc707-xc7vx485t/socmap.vhd:477]
ERROR: [Synth 8-1031] cache_tile_id is not declared [/projects/esp/socs/xilinx-vc707-xc7vx485t/socmap.vhd:478]
ERROR: [Synth 8-1031] cache_tile_id is not declared [/projects/esp/socs/xilinx-vc707-xc7vx485t/socmap.vhd:480]
After reverting to an older commit c462c99, everything is working fine. I did not try any version in between though.
Thank you for the advice, the problem is fixed. But there is another problem when i boot linux:
Disabling lock debugging due to kernel taint
Caller[f0108428]: __register_sysctl_table+0x35c/0x514
Caller[f04f5eec]: ipv4_sysctl_init_net+0x14/0x68
Caller[f02e0ab8]: ops_init.constprop.7+0xac/0x148
Caller[f02e0c04]: register_pernet_operations+0xb0/0x104
Caller[f02e0c70]: register_pernet_subsys+0x18/0x34
Caller[f04f5eb4]: sysctl_ipv4_init+0x34/0x58
Caller[f0007128]: do_one_initcall+0x2c/0x174
Caller[f04df01c]: kernel_init_freeable+0x124/0x1c0
Caller[f03e0b14]: kernel_init+0x4/0x104
Caller[f0008234]: ret_from_kernel_thread+0xc/0x38
Caller[00000000]: (null)
Instruction DUMP: 80886001
12800076 01000000
< c6006004> 88106001
80a0c002 0280002c
8e100001 80a0e000
Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009
Press Stop-A (L1-A) to return to the boot prom
---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009
Originally posted by @CristinaZN in #50 (comment)
Describe the bug
The accelerator L2 wrapper issues a flush to the L2 before the last requests are served. Because of the priority encoding in the cache, the flush is processed before CPU requests. This breaks coherence assumptions that an accelerator is exclusively working on data, and triggers undefined behavior with later DMA requests.
To Reproduce
Steps to reproduce the behavior:
On branch esp-synth-app, create an SoC with 12 synthetic accelerators. Run the application synth.exe with the file synth_cfg.txt .
Expected behavior
The flush should not be issued until the final request has been served.
Currently we do not own any of the supported platforms but we are interested in adding ESP to our workflow. We do have other FPGA boards we would like to use.
I was wondering how easy would it be to add support for additional platforms. Namely the ZCU102 and Alveo U280.
Alternatively, I could try to generate the required files on my own but I do not see a tutorial or guide on that.
Thanks in advance.
Describe the bug
On CentOS 7 the accelerator generation script utils/scripts/init_accelerator.sh
fails after executing the last interactive step.
Here is the error message:
rename: accelerator.h: rename to cholesky.h failed: No such file or directory
If bumping Ariane to include PMP support, we see a kernel panic when attempting to run init.
Moving discussion from #61
The accelerator nodes in Ariane's device tree are generated incorrectly:
memory-region
field for reserved memory. Only third party accelerators should have that, e.g. NVDLA.I'm trying to reproduce the SoC for the VCU118 board. After enabling 1000 MBit support for the Ethernet peripheral, Vivado implementation will fail with the following messages:
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xcvu9p'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcvu9p'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
ERROR: [DRC INBB-3] Black Box Instances: Cell 'eth0.e1/m1000.u0/gtxc0' of type 'greth_gbitc' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
INFO: [Project 1-461] DRC finished with 1 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 8333.207 ; gain = 47.984 ; free physical = 23609 ; free virtual = 25108
INFO: [Common 17-83] Releasing license: Implementation
19 Infos, 1 Warnings, 1 Critical Warnings and 2 Errors encountered.
opt_design failed
opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 8333.207 ; gain = 48.016 ; free physical = 23609 ; free virtual = 25108
ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.
INFO: [Common 17-206] Exiting Vivado at Thu Jun 4 16:36:32 2020...
[Thu Jun 4 16:36:33 2020] impl_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : 'impl_1'
ERROR: bistream not found; synthesis failed
The menu for the 1000 MBit option in make grlib-xconfig
:
I'm relaunching the flow without 1000 MBit support to see if this is the problem, the synthesis is spinning now.
Update: things went past DRC with 1000 MBit support off. Seems like an issue with the GbE MAC IP?
Describe the bug
On a small screen part of the ESP GUI doesn't fit the screen and it can't be accessed in any way. This for example prevents from saving the configuration with the button at the bottom.
To Reproduce
An a medium/small laptop go to one of the subfolders of socs
and run make esp-xconfig
.
Expected behavior
Ideally there should be vertical and horizontal scrollbars to access the parts of the GUI that don't fit the screen.
When generating accelerators with the ESP interactive script, the automatically generated device driver cannot be registered by Linux when using the Leon3 processor core. The device driver probe doesn't even get called.
Hello,
I saw on the website cache isn't implemented yet for Ariane. Is that still the case? Is there any branches that I could test out that uses cache?
Thank you!
NVDLA is not leveraging AXI burst: all transactions have length set to 1 beat.
This is not ideal to communicate over the NoC with the current implementation of the AXI proxy.
We need to allow the AXI proxy to handle multiple outstanding transactions. The number of transactions should be configurable at design time and result in the instance of a queue to hold the necessary information to process DMA read responses.
In addition, the DMA engine must be split into two separate processes to handle requests and responses in parallel.
Moving discussion from #61
Is your feature request related to a problem? Please describe.
There is no application to invoke the Chisel accelerator AdderAccelerator
Describe the solution you'd like
An example application should be implemented.
Due to some recent CentOS 7 update the binutils
step of the Leon3 toolchain initialization: utils/scrips/build_leon3_toolchain.sh
.
The following sequence of flits is not routed correctly. In the sequence I use the processor port (P), the west port (W) and the north port (N), but the bug can be triggered using different ports, as long as the output port is the same for all the flits.
Device drivers, including bare metal applications, should be able to probe the hardware and detect whether the ESP cache hierarchy is present and whether the accelerator has the private L2 cache in the tile.
After probe, this information should be stored in the device data structure and used to prevent invocations with coherence models not enabled in the current hardware configuration.
make sim
, before setting CAD tools environment requires a make sim-distclean
to enable correct compilation.
Buildroot Build Issue
I tried to re-setup the ESP environment from the beginning.
git clone --recursive https://github.com/sld-columbia/esp.git
cd esp
./utils/toolchain/build_riscv_toolchain.sh
Then I encountered the following error at last step, "Populating root file system w/ buildroot".
...
...
>>> host-attr 2.4.48 Configuring
(cd /tmp/_riscv_build/buildroot/output/build/host-attr-2.4.48/ && rm -rf config.cache; PATH="/tmp/_riscv_build/buildroot/output/host/bin:/tmp/_riscv_build/buildroot/output/host/sbin:/opt/riscv/bin:/home/aie/.local/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin" PKG_CONFIG="/tmp/_riscv_build/buildroot/output/host/bin/pkg-config" PKG_CONFIG_SYSROOT_DIR="/" PKG_CONFIG_ALLOW_SYSTEM_CFLAGS=1 PKG_CONFIG_ALLOW_SYSTEM_LIBS=1 PKG_CONFIG_LIBDIR="/tmp/_riscv_build/buildroot/output/host/lib/pkgconfig:/tmp/_riscv_build/buildroot/output/host/share/pkgconfig" AR="/usr/bin/ar" AS="/usr/bin/as" LD="/usr/bin/ld" NM="/usr/bin/nm" CC="/tmp/_riscv_build/buildroot/output/host/bin/ccache /usr/bin/gcc" GCC="/tmp/_riscv_build/buildroot/output/host/bin/ccache /usr/bin/gcc" CXX="/tmp/_riscv_build/buildroot/output/host/bin/ccache /usr/bin/g++" CPP="/usr/bin/cpp" OBJCOPY="/usr/bin/objcopy" RANLIB="/usr/bin/ranlib" CPPFLAGS="-I/tmp/_riscv_build/buildroot/output/host/include" CFLAGS="-O2 -I/tmp/_riscv_build/buildroot/output/host/include" CXXFLAGS="-O2 -I/tmp/_riscv_build/buildroot/output/host/include" LDFLAGS="-L/tmp/_riscv_build/buildroot/output/host/lib -Wl,-rpath,/tmp/_riscv_build/buildroot/output/host/lib" INTLTOOL_PERL=/usr/bin/perl CFLAGS="-O2 -I/tmp/_riscv_build/buildroot/output/host/include" LDFLAGS="-L/tmp/_riscv_build/buildroot/output/host/lib -Wl,-rpath,/tmp/_riscv_build/buildroot/output/host/lib" CONFIG_SITE=/dev/null ./configure --prefix="/tmp/_riscv_build/buildroot/output/host" --sysconfdir="/tmp/_riscv_build/buildroot/output/host/etc" --localstatedir="/tmp/_riscv_build/buildroot/output/host/var" --enable-shared --disable-static --disable-gtk-doc --disable-gtk-doc-html --disable-doc --disable-docs --disable-documentation --disable-debug --with-xmlto=no --with-fop=no --disable-dependency-tracking --disable-nls )
configure: WARNING: unrecognized options: --disable-gtk-doc, --disable-gtk-doc-html, --disable-doc, --disable-docs, --disable-documentation, --with-xmlto, --with-fop
checking for a BSD-compatible install... /usr/bin/install -c
checking whether build environment is sane... yes
checking for a thread-safe mkdir -p... /bin/mkdir -p
checking for gawk... gawk
checking whether make sets $(MAKE)... yes
checking whether make supports nested variables... yes
checking whether make supports nested variables... (cached) yes
checking for gcc... /tmp/_riscv_build/buildroot/output/host/bin/ccache /usr/bin/gcc
checking whether the C compiler works... yes
checking for C compiler default output file name... a.out
checking for suffix of executables...
checking whether we are cross compiling... no
checking for suffix of object files... configure: error: in `/tmp/_riscv_build/buildroot/output/build/host-attr-2.4.48':
configure: error: cannot compute suffix of object files: cannot compile
See `config.log' for more details
package/pkg-generic.mk:219: recipe for target '/tmp/_riscv_build/buildroot/output/build/host-attr-2.4.48/.stamp_configured' failed
make: *** [/tmp/_riscv_build/buildroot/output/build/host-attr-2.4.48/.stamp_configured] Error 1
I wonder what may be the issue? Please advise.
Thanks a lot in advance.
Is your feature request related to a problem? Please describe.
I have an existing accelerator implementation in Verilog, and I would like to port it to ESP infrastructure, so that I can use the ESP toolchain with Vivado tools.
The website says
Other options include designing the accelerator in RTL (Verilog, VHDL, SystemVerilog) or designing a deep learning accelerator in Keras/Pytorch/ONNX by leveraging hls4ml. These other options don’t have full support in ESP yet. It’s possible to use them, but they will require more integration effort.
Describe the solution you'd like
If there are any examples or advice (it sounds like there might be from the above quotation?) on doing that, I would appreciate those resources. I would document and contribute back my process once I get it to work.
Describe alternatives you've considered
I am currently trying to work through accelerators/vivado_hls/common/syn/common.tcl
and convert that to a version which accepts Verilog input, but this is not my strongsuit.
This is a request for documentation, not a feature request per se, but I am posting it here instead of in an email so that those who encounter this problem in the future can see this issue.
Describe the bug
Device drivers incorrectly configure accelerators with more that 4 configuration parameters. The p2p-related functions in the driver most likely have a buffer overflow.
To Reproduce
Create any ESP accelerator with more than four configuration parameters and test it on FPGA.
Expected behavior
Currently ESP works with up to 14 custom configuration parameters per accelerator.
FPGA prototype step of guide "How to: design a single-core SoC" fails when trying to synthesize mig and sgmii
To reproduce, follow the steps in the How to: design a single-core SoC" guide until the FPGA pretty step.
I expected to be able to complete the example without any issues.
See screenshot of errors:
Latest Linux kernels may have issues booting with BBL
The ideal solution would be to replace the boot loader with OpenSBI.
Describe the bug
During SMAD(W) transition, when receiving an FWD_INV from NoC, ESP L2 does not send an INVAL to in-tile L1. This can cause erroneous behavior when multicores write to different words in same cache line (MESI false sharing).
To Reproduce
Steps to reproduce the behavior:
Expected behavior
Core 0 should print results from the all the tests. However, system hangs after printing "Start testing on 4 CPUs." Although I am not 100% sure if this is actually caused by the reported bug, but this behavior was identical to Spandex before the above bug was fixed by inserting inval(fwd_in.addr) to L1.
Desktop (please complete the following information):
Additional context
See email thread with subject ESP L1 Invalidations
Vivado HLS may generate Xilixn IP definition files (.xci) as part of the generated RTL.
Currently, ESP installs only RTL and data (.dat) files into the technology-dependent folder.
Users can work around this issue by adding manually the xci file to the list of source files for synthesis, but ESP should pick these files automatically with the Make target <accelerator>-hls
and make vivado/srcs.tcl
Currently the soft-reset is only resetting the processor cores and the ESP cache hierarchy.
Other components, such as the timer and the interrupt controller, should be reset to make sure that a reboot can occur without reprogramming the FPGA.
For now, the target fpga-run-linux depends on fpga-program, but it would be nice to remove such dependency.
Bare metal applications with large memory footprints cannot be easily simulated.
Increasing the size of ahbram_sim
beyond a few MB slows down the RTL simulator.
Furthermore, when RISC-V is selected, accelerators operate on a memory region with high base address. This region is not represented in the current memory model.
Simulations still work in most cases, because addresses wrap around, as long the result of wrap around does not conflict with the location of the program, or its data.
Proposed solution
Any access to the DRAM model in ahbram_sim
should not access an RTL array. Instead, operations should be redirected to a C-based model. Allocated memory regions should be represented as a hash table for quick access to the entire address space, with little memory footprint for the host.
The ESP xconfigurator says that the maximum supported number of tiles is 64. However the number of bits used to index the tiles in nockpackage is 5 bits. https://github.com/sld-columbia/esp/blob/master/rtl/include/sld/noc/nocpackage.vhd#L36
If someone instantiates an SOC of 64 X 1, ESP xconfigurator lets it pass but the NOC might get confused.
Bug already reported in email to
Paolo Mantovani [email protected]
Davide Giri [email protected]
Hello,
I got this error when simulating ESP. Can anyone help?
** Error: /mnt/Archive/Downloads/esp/rtl/src/techmap/unisim/tap_unisim.vhd(30): (vcom-1598) Library "unisim" not found.
** Error: /mnt/Archive/Downloads/esp/rtl/src/techmap/unisim/tap_unisim.vhd(31): (vcom-1136) Unknown identifier "unisim".
** Note: /mnt/Archive/Downloads/esp/rtl/src/techmap/unisim/tap_unisim.vhd(34): VHDL Compiler exiting
make: *** [/mnt/Archive/Downloads/esp/utils/Makefile:1174: modelsim/vsim.mk] Error 2
Add configuration knob for the Leon3 stack pointer.
We used to configure this through GRMON, however the latest release of the evaluation version does not allow us to connect to the debug unit when the system integrates IP blocks not recognized by GRMON.
We've implemented our own open-source application to replace GRMON, but at the moment we cannot manage the Leon3 debug unit.
Describe the bug
When testing ESP on FPGA, for an unknown reason sometimes the Vivado HLS accelerators do not function correctly. When adding debug probes with the Vivado ILA utility to the accelerator interface, the accelerators always function correctly.
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