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alloy-asic

alloy-asic -- The Modular VLSI Build System

amba_apb_sram

AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

amc

AMC: Asynchronous Memory Compiler

anasymod

A framework for FPGA emulation of mixed-signal systems

args

A simple header-only C++ argument parser library. Supposed to be flexible and powerful, and attempts to be compatible with the functionality of the Python standard argparse library (though not necessarily the API).

armor

autosub

Command-line utility to transcribe/translate from video/audio/subtitles to subtitles

autosva

AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.

backstroke

A tool for reversible computation in C++ based on incremental state saving.

bag_framework

Berkeley Analog Generator

bag_framework-1

Berkeley Analog Generator

barchart

a simple gnuplot (>= 5.0) front-end for generating bar charts

bargraph

Clustered/Stacked Filled Bar Graph Generator

basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

bsg_fakeram

fakeram generator for use by researchers who do not have access to commercial ram generators

bsg_manycore

Tile based architecture designed for computing efficiency, scalability and generality

bsg_sv2v

calipers

Criticality-aware Framework for Modeling Computer Performance

captive

The Captive Hypervisor

cascade

A Just-In-Time Compiler for Verilog from VMware Research

cash

A C++ Library for Hardware Design and Simulation

ccicheck

charm

The Charm++ parallel programming system. Visit http://charmplusplus.org/ for more information.

chronos

The Chronos FPGA Framework to accelerate ordered applications

clang-extract

Like GCC-XML for clang. Clang-extract is an AST pass which outputs an easily parsed description of the source.

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

cosmos-openssd

cosmos-plus-openssd

Cosmos OpenSSD + Hardware and Software source distribution

ctypeslib

Generate python ctypes classes from C headers. Requires LLVM clang

custom-riscv-tracer

RISC-V tracer