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ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

awesome-open-hardware-verification

A List of Free and Open Source Hardware Verification Tools and Frameworks

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

basic_verilog

Must-have verilog systemverilog modules

bert-pytorch

Google AI 2018 BERT pytorch implementation

candle

Minimalist ML framework for Rust

common_cells

Common SystemVerilog components

esp

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

gemmini

Berkeley's Spatial Array Generator

gvsoc

llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this moment. Please submit your patches at http://reviews.llvm.org.

nyuziprocessor

GPGPU microprocessor architecture

rcore-tutorial-v3

Let's write an OS which can run on RISC-V in Rust from scratch!

riscv-isa-sim

Spike, a RISC-V ISA Simulator

rocm-examples

rv12

RISC-V CPU Core

scale-sim-v2

Repository to host and maintain scale-sim-v2 code

scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

snitch

Lean but mean RISC-V system!

spatz

Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.

style-guides

lowRISC Style Guides

verilog-perl

Verilog parser, preprocessor, and related tools for the Verilog-Perl package