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bus-arbiter-using-round-robin-method

a verilog based implementation of bus arbitration scheme

cache-sim

cache simulator

cachelru_simulation

cmos_standard_cell_library

CMOS standard cell library (schematic and layout) using Electric VLSI and SPICE sim, Spring 18

common_cells

Common SV components

cts_paper_reproduction

reproduction paper research in low voltage clock tree design

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

dram_adaptiverefresh

A proposal of new adaptive refresh mechanism and its verification

dvb_fpga

RTL implementation of components for DVB-S2

ecc_hardware

Hardware implementation of Error-Correction Code in Verilog

ece5745-tut5-asic-tools

ECE 5745 Tutorial 5: Synopsys/Cadence ASIC Tools

esp

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

generic_sram_apb

RTL design of a generic SRAM module with APB I/F.

ib_layerldpc_asymaccess_memshare

Enhancement of InformationBottleneck Implementation on FPGAs

informationbottleneck_rtl_generator

A HDL code generator to construct the Information Bottleneck based LDPC decoder architecture on FPGAs

intra-task-dvfs-simulator

A cycle-accurate simulator for hard real-time system for my master thesis. It perform Intra-task DVFS behaviour within execution of periodic tasks aiming at reducing response time jitter and energy consumption.

last-level-cache-simulator

ldpc-decoder

Design and RTL implementation of an LDPC decoder.

learning_analogic

This repository is to keep the record of all my learning of analogue circuit.

ltspice-basics

A set of simulation exercises to get you up and running with LTspice

multicorecache_sim

A simple simulator for evaluating the hit/miss ratio of L1 data cache under multicore system with one main memory.

nand-flash-memory-controller-verification

nvm-flash-memory-channel-simulation

NVM Flash Memory Channel Simulation/ISE MATLAB Modelsim

qc_ldpc_construction_optimisation

A framework of constructing Quasi-Cyclic LDPC Codes using some optimisation approaches.

ramulator

A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf

realtime_sched

reed-solomon

Reed-Solomon encoder in SystemVerilog

risc-v-project

This is a simple exercise of implementing microprocessor based on RISC-V instruction set.

riscv-decoder

Python-based RISC-V decoder and verifier

riscv_reference

RISC-V CPU Core (RV32IM)