Comments (4)
If it's not clear, we need to clarify it!
Right now the description is here: https://github.com/riscv/riscv-debug-spec/blob/0.13/debug_module.tex#L101
and here:
https://github.com/riscv/riscv-debug-spec/blob/0.13/xml/dm_registers.xml#L89
The intent is that once a hart is halted, it doesn't matter what you write to haltreq (1 or 0). But, if the hart runs again (because you did a resume, or reset) then what is contained in haltreq matters, so you should write it to 0 before doing resumereq (it does say that is undefined), or 1 or 0 during reset depending on what you want to happen when hart comes out of reset.
from riscv-debug-spec.
Thanks for your quick reply. I only looked at the table before. After I see the description in 3.4, it's quite clear to me now.
However, I have a question about resumeack. If a resumeack has no effect on a hart which is running, why could it cause a hart which halts in the future to immediately resume?
https://github.com/riscv/riscv-debug-spec/blob/0.13/debug_module.tex#L129
The spec mention that the debugger should not depend on that behavior, but that sentence(L129) is kind of self-contradictory. Do you feel the same thing?
from riscv-debug-spec.
Yes, I think the statement that "resumereq has no effect on hart which is running" is probably the wrong part. I think it should say that debuggers should not do this, because its effect on harts which are running or will halt in the future is undefined. What do you think?
Also, there was another question on the mailing list about this section. I realized the part that is in a comment might be read as referring to what debugger should do on both halt and resume, when it really only means what it should do on resume:
https://github.com/riscv/riscv-debug-spec/blob/0.13/debug_module.tex#L121. We should either clarify or remove this comment.
from riscv-debug-spec.
I have attempted to make this more clear in the latest version of the spec.
from riscv-debug-spec.
Related Issues (20)
- A typo in [5.4. Native Triggers] HOT 1
- How to halt or resume multiple harts simultaneously? HOT 4
- Stored value availability to TM in case of AMOs HOT 6
- Hit bit interaction with action conflict when several triggers of the same priority match HOT 3
- How to reset the DM on the first connection on both 0.13 and 1.0 spec versions HOT 7
- Cross Trigger definition in RISC-V HOT 3
- Trigger match on csrrs/csrrc to tdata1 HOT 13
- Why debugger lose control of the hart while executing a program not terminate with an ebreak instruction
- Ambiguous requirement about dmcontrol behavior when dmcontrol.dmactive==0 HOT 2
- Minor typo + Cannot open PR HOT 2
- Multiple mcontrol6 triggers match on same instruction with different actions and timings HOT 1
- Can tselect be written with an invalid index HOT 2
- Value of tinfo when selected trigger does not exist HOT 2
- Missing state names HOT 1
- Are the vs and vu bits in mcontrol6 dependent on misa.h? HOT 2
- Question about mcontrol6.match and tdata2 HOT 4
- make list of implementation options
- Clarify apparent inconsistency of debug version read by registers
- dcsr.cetrig should be WARL HOT 1
- Question about trigger exceptions and other types of exceptions occurring at the same time HOT 8
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from riscv-debug-spec.