Comments (2)
Everything in the DM is held in reset except for the dmactive bit itself. Because the DM is in reset, it must not allow any state to contain the non-reset value (which is your second variant). The very next sentence says "Any accesses to the module may fail" which means that the external debugger shouldn't be doing any writes at all (of any values, including the reset values).
from riscv-debug-spec.
@pdonahue-ventana, thank you for the clarification.
from riscv-debug-spec.
Related Issues (20)
- A typo in [5.4. Native Triggers] HOT 1
- How to halt or resume multiple harts simultaneously? HOT 4
- Stored value availability to TM in case of AMOs HOT 6
- Hit bit interaction with action conflict when several triggers of the same priority match HOT 3
- How to reset the DM on the first connection on both 0.13 and 1.0 spec versions HOT 7
- Cross Trigger definition in RISC-V HOT 3
- Trigger match on csrrs/csrrc to tdata1 HOT 13
- Why debugger lose control of the hart while executing a program not terminate with an ebreak instruction
- Minor typo + Cannot open PR HOT 2
- Multiple mcontrol6 triggers match on same instruction with different actions and timings HOT 1
- Can tselect be written with an invalid index HOT 2
- Value of tinfo when selected trigger does not exist HOT 2
- Missing state names HOT 1
- Are the vs and vu bits in mcontrol6 dependent on misa.h? HOT 2
- Question about mcontrol6.match and tdata2 HOT 4
- make list of implementation options
- Clarify apparent inconsistency of debug version read by registers
- dcsr.cetrig should be WARL HOT 1
- Question about trigger exceptions and other types of exceptions occurring at the same time HOT 8
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