Are the vs and vu bits in mcontrol6 dependent on misa.h? about riscv-debug-spec

[rtwfroody]

@pdonahue-ventana mentioned in email:

Take a look at the definition of misa. If misa.h=0 then it's supposed to behave exactly as if H isn't implemented at all. That means that vu/vs should be read-only 0.

[rtwfroody]

This text was probably written without considering that misa.h is writable. The answer hinges on what it means to support a virtualization mode. Does the ISA spec define that term?

To me it makes most sense to consider whether the feature is implemented, regardless of whether it is currently enabled. Further support for that idea is that the intro to section 5.7 says "Almost all trigger functionality is optional" and does not explicitly mention that the supported features may depend on other hart state.

For the debugger it would be simpler to always allow setting vu regardless of misa, since it makes discovery easier. Changing what triggers can be set depending on misa is just more to keep track of.