Contains all project code found on www.nandland.com
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License: MIT License
SPI Slave for FPGA in Verilog and VHDL
License: MIT License
Contains all project code found on www.nandland.com
w_CPOL assigned a value but never read
Hi,
I've been trying to get this library to work on an Ice40 FPGA with Icestorm,
it -really- doesn't want to work thanks to the ' or posedge i_SPI_CS_n' of line 154.
On removal, it will compile, but then comms is wrong, likely due to the CS triggering at the wrong time.
Is there a possibility of a fix on this?
yosys -p "synth_ice40 -blif hardware.blif" -q comm_fpga_spi.v main.v
Warning: Yosys has only limited support for tri-state logic at the moment. (comm_fpga_spi.v:194)
Warning: reg '\o_SPI_MISO' is assigned in a continuous assignment at comm_fpga_spi.v:194.
Warning: Async reset value `\r_TX_Byte [7]' is not constant!
arachne-pnr -d 5k -P sg48 -p up5k.pcf -o hardware.asc -q hardware.blif
hardware.blif:116: fatal error: unknown model `$_DFFSR_PPP_'
scons: *** [hardware.asc] Error 1
Since the controller (FPGA) and SPI work on different clock domains, the controller needs to know when it can send another byte on MISO to avoid causing buffer overruns.
Both the 'transmitter' and 'receiver' procedural blocks execute at the same edge (posedge w_SPI_Clk
).
This cannot be correct, flipping must occur before the master performs its sampling.
GowinSynthesis reports an implicit latch at
spi-slave/Verilog/source/SPI_Slave.v
Line 167 in e12af34
WARN (DI0003) : Latch inferred for net 'r_SPI_MISO_Bit';We do not recommend the use of latches in FPGA designs, as they may lead to timing problems("spi_slave.v":167)
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