litex-hub / linux-on-litex-rocket Goto Github PK

View Code? Open in Web Editor NEW

107.0 107.0 15.0 40 KB

Run 64-bit Linux on LiteX + RocketChip

License: BSD 2-Clause "Simplified" License

linux-on-litex-rocket's People

Contributors

Stargazers

Watchers

Forkers

shaneutt hasheddan mfkiwl jluebbe a937983423 troibe tretter kchenlab yummy0929 orkunaliozkan pcotret drawson5570

linux-on-litex-rocket's Issues

Uploading binary fails at BAUD rates over 230400

I'm not quite sure what is causing this but I tried different BAUD rates on the Arty.
When using LiteX+BlackParrot I can upload at BAUD rates up to 921600.
This makes it easy to use LiteScope over Ethernet and still have decent upload speed over UART.

serialboot
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
[LXTERM] Received firmware download request from the device.
[LXTERM] Uploading boot-arty-success.bin to 0x80000000 (15705408 bytes)...
[LXTERM] Upload to device failed due to data corruption (CRC error)

Unable to boot into linux on simulated SoC - Kernel panic

Hello there!

I'm building LiteX SoC with a single rocket core on litex_sim using self made dependencies.

The steps taken to build my dependencies are the following:

generate the csr file using litex_sims support
Convert the csr into a dt file
Convert the dt file into a device tree blob file
Build busybox
Create kernel root ram filesystem
Build the kernel
Build fw_jump
Run the simulator (preloading these dependencies)

Please find attached bellow the console log bellow, so you can see how far into the boot I reach:
consolelogkernelpanic.txt

The notable lines of reference however are the following:

[    5.581115] Freeing unused kernel image (initmem) memory: 2816K
[    5.583210] Run /init as init process
[    5.583693]   with arguments:
[    5.583965]     /init
[    5.584206]   with environment:
[    5.584455]     HOME=/
[    5.584687]     TERM=linux
[    5.594537] Failed to execute /init (error -2)
[    5.595162] Run /sbin/init as init process
[    5.595487]   with arguments:
[    5.595737]     /sbin/init
[    5.595986]   with environment:
[    5.596214]     HOME=/
[    5.596461]     TERM=linux
[    5.602636] Run /etc/init as init process
[    5.603198]   with arguments:
[    5.603467]     /etc/init
[    5.603698]   with environment:
[    5.603945]     HOME=/
[    5.604176]     TERM=linux
[    5.609673] Run /bin/init as init process
[    5.610292]   with arguments:
[    5.610574]     /bin/init
[    5.610827]   with environment:
[    5.612462]     HOME=/
[    5.612899]     TERM=linux
[    5.618560] Run /bin/sh as init process
[    5.619160]   with arguments:
[    5.619467]     /bin/sh
[    5.619713]   with environment:
[    5.619959]     HOME=/
[    5.620187]     TERM=linux
[    5.627298] Kernel panic - not syncing: No working init found.  Try passing init= option to kernel. See Linux Documentation/admin-guide/init.rst for guidance.
[    5.628017] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 6.3.0-rc5-gff903dea5e37 #6
[    5.628478] Call Trace:
[    5.628762] [<ffffffff8000502e>] dump_backtrace+0x1c/0x24
[    5.629415] [<ffffffff804b21c6>] show_stack+0x2c/0x38
[    5.630052] [<ffffffff804b9b1c>] dump_stack_lvl+0x3c/0x54
[    5.630696] [<ffffffff804b9b48>] dump_stack+0x14/0x1c
[    5.631265] [<ffffffff804b235e>] panic+0xf8/0x284
[    5.631833] [<ffffffff804ba194>] __irq_alloc_descs+0x0/0x1fa
[    5.632385] [<ffffffff80003234>] ret_from_exception+0x0/0x16
[    5.632991] ---[ end Kernel panic - not syncing: No working init found.  Try passing init= option to kernel. See Linux Documentation/admin-guide/init.rst for guidance. ]---

I did a bit of reading on this error and found the following document discussed the issue quite well: https://docs.kernel.org/admin-guide/init.html

Any help would be much appreciated ^^

Prebuilt Binaries: bitstreams, boot images, intermediate software components

Bitstream for nexys4ddr, trellisboard, ecpix5, and versa_ecp5:

Boot images for nexys4ddr, trellisboard, ecpix5, versa_ecp5, and Verilator-based simulation:

Initial RAM filesystem image to be embedded into the Linux kernel during build (contains busybox binary and directory structure):

initramfs.cpio.gz

NOTE: The resulting vmlinux kernel to be embedded into BBL (to obtain boot.bin) is currently too large (110M) to be allowed as an attachment here (even using xz compression, vmlinux.xz is 25M, which still exceeds the 10M limit). Sorry, for now you'll have to build this one on your own!

Booting into linux on simulation

At the moment, I'm not aware of a good way to tell the firmware/BIOS to simply jump to the first RAM address and start executing the side-loaded boot.bin which is now located there. Although that should be an easy fix.

For linux-on-litex-blackparrot we are setting the ROM_BOOT_ADDRESS in litex_sim.py to 0x80000000.
However even with that change I didn't manage to boot into linux with rocket.
Do you have exact steps that you followed to accomplish that?
Using a method other than side loading would be fine as well of course.

I just want to make sure that I'm having a reproducible boot into linux in simulation before I further attempt it on my ulx3s and arty7.
For the ulx3s so far I'm reliably getting into the bios. On the arty7 I encounter some memory errors with newer versions of litex.

Design doesn't fit on OrangeCrab FPGA

I'd really like to be able to run this on the OrangeCrab, which has an EPC5 LFE5U-25F. Unfortunately, it uses 20,360 TRELLIS_SLICE blocks, but the board only has 12,144 of them. Are there any optimizations that could be made to fit this onto a smaller FPGA? Is the Rocket core the smallest possible that is capable of running Linux? Could more functionality be optionally removed from it and emulated in BBL?

genesys2: full4q CPU variant not supported

Following the instructions for building for the Digilent Genesys2 ...

litex-boards/litex_boards/targets/digilent_genesys2.py --build \
    --cpu-type rocket --cpu-variant full4q --sys-clk-freq 100e6 \
    --with-ethernet --with-sdcard

... I get the following error:

1.057 ERROR:SoC:full4q CPU variant not supported, supported are:
1.057  - full
1.057  - linux
1.057  - medium
1.057  - small

I am wondering whether I should use full or linux instead of full4q? Or maybe I made some error installing litex.

Your help is greatly appreciated.

Set up on Ubuntu might be incomplete

My x64 host is running Ubuntu 21.04 (Hirsute Hippo), fully up to date. I tried to map the step 1 to equivalent Ubuntu repos (I would need to this on a clean installation to complete this).

$ sudo apt install libjson-c-dev libcrypt-openssl-bignum-perl libevent-dev libmpc-dev libmpfr-dev python3-dev

but step python3 ./litex_setup.py init install --user fails with

$ python3 ./litex_setup.py init install --user
[checking litex_setup.py]...
[installing migen]...
Traceback (most recent call last):
  File "/home/tommy/projects/migen/setup.py", line 4, in <module>
    from setuptools import setup
ModuleNotFoundError: No module named 'setuptools'
Traceback (most recent call last):
  File "/home/tommy/projects/linux-on-litex-rocket/./litex_setup.py", line 168, in <module>
    subprocess.check_call("python3 setup.py develop --user", shell=True)
  File "/usr/lib/python3.9/subprocess.py", line 373, in check_call
    raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command 'python3 setup.py develop --user' returned non-zero exit status 1.

How to determine bit width of the point-to-point AXI link?

I'm trying to run your project on an ULX3S however I'm now wondering what the appropriate bit width would be.
Is there some table with the bit width of all supported litex boards?
Where did you find this information?

Boot hang with DE2-115

Hello,
I'm trying with Altera DE2-115 kit. I have added ethernet patch to make TFTP boot work. However, the booting is hang at step Freeing unused kernel image (initmem) memory: 2708K
For the dts file, as the guide here #8
I made a copy of arty.dts, update few sessions

Update the right address for UART
Update RAM size
Update session related to soc, ethernet, uart with output from litex_json2dts.py
de2-115.dts.txt
csr.json.txt

This is the boot log. Could you please give me few hints on checking this issue?
Thank you!

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2022 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Feb 11 2022 07:16:50
 BIOS CRC passed (608dacb6)

 Migen git sha1: ac70301
 LiteX git sha1: 7cc781f7

--=============== SoC ==================--
CPU:            RocketRV64[imac] @ 50MHz
BUS:            WISHBONE 32-bit @ 4GiB
CSR:            32-bit data
ROM:            128KiB
SRAM:           8KiB
SDRAM:          65536KiB 16-bit @ 50MT/s (CL-2 CWL-2)

--========== Initialization ============--
Ethernet init...
Initializing SDRAM @0x80000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x80000000 (2.0MiB)...
  Write: 0x80000000-0x80200000 2.0MiB     
   Read: 0x80000000-0x80200000 2.0MiB     
Memtest OK
Memspeed at 0x80000000 (Sequential, 2.0MiB)...
  Write speed: 5.8MiB/s
   Read speed: 9.7MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
Booting from network...
Local IP: 192.168.1.50
Remote IP: 192.168.1.100
Booting from boot.json...
Booting from boot.bin...
Copying boot.bin to 0x80000000... (17824296 bytes)
Executing booted program at 0x80000000

--============= Liftoff! ===============--
bbl loader
              vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
                  vvvvvvvvvvvvvvvvvvvvvvvvvvvv
rrrrrrrrrrrrr       vvvvvvvvvvvvvvvvvvvvvvvvvv
rrrrrrrrrrrrrrrr      vvvvvvvvvvvvvvvvvvvvvvvv
rrrrrrrrrrrrrrrrrr    vvvvvvvvvvvvvvvvvvvvvvvv
rrrrrrrrrrrrrrrrrr    vvvvvvvvvvvvvvvvvvvvvvvv
rrrrrrrrrrrrrrrrrr    vvvvvvvvvvvvvvvvvvvvvvvv
rrrrrrrrrrrrrrrr      vvvvvvvvvvvvvvvvvvvvvv  
rrrrrrrrrrrrr       vvvvvvvvvvvvvvvvvvvvvv    
rr                vvvvvvvvvvvvvvvvvvvvvv      
rr            vvvvvvvvvvvvvvvvvvvvvvvv      rr
rrrr      vvvvvvvvvvvvvvvvvvvvvvvvvv      rrrr
rrrrrr      vvvvvvvvvvvvvvvvvvvvvv      rrrrrr
rrrrrrrr      vvvvvvvvvvvvvvvvvv      rrrrrrrr
rrrrrrrrrr      vvvvvvvvvvvvvv      rrrrrrrrrr
rrrrrrrrrrrr      vvvvvvvvvv      rrrrrrrrrrrr
rrrrrrrrrrrrrr      vvvvvv      rrrrrrrrrrrrrr
rrrrrrrrrrrrrrrr      vv      rrrrrrrrrrrrrrrr
rrrrrrrrrrrrrrrrrr          rrrrrrrrrrrrrrrrrr
rrrrrrrrrrrrrrrrrrrr      rrrrrrrrrrrrrrrrrrrr
rrrrrrrrrrrrrrrrrrrrrr  rrrrrrrrrrrrrrrrrrrrrr

       INSTRUCTION SETS WANT TO BE FREE
[    0.000000] Linux version 5.17.0-rc3-g9416933b8c5f (administrator@sm06) (riscv64-unknown-linux-gnu-gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.36.1) #3 SMP Fri Feb 11 10:19:30 UTC 2022
[    0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000
[    0.000000] Machine model: freechips,rocketchip-unknown
[    0.000000] earlycon: liteuart0 at I/O port 0x0 (options '')
[    0.000000] Malformed early option 'console'
[    0.000000] earlycon: liteuart0 at MMIO 0x0000000012003000 (options '')
[    0.000000] printk: bootconsole [liteuart0] enabled
[    0.000000] efi: UEFI not found.
[    0.000000] Zone ranges:
[    0.000000]   DMA32    [mem 0x0000000080200000-0x0000000083ffffff]
[    0.000000]   Normal   empty
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000080200000-0x0000000083ffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x0000000083ffffff]
[    0.000000] SBI specification v0.1 detected
[    0.000000] riscv: ISA extensions acdfim
[    0.000000] riscv: ELF capabilities acdfim
[    0.000000] percpu: Embedded 13 pages/cpu s24088 r0 d29160 u53248
[    0.000000] pcpu-alloc: s24088 r0 d29160 u53248 alloc=13*4096
[    0.000000] pcpu-alloc: [0] 0 
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 15624
[    0.000000] Kernel command line: console=liteuart earlycon=liteuart,0x12003000 swiotlb=noforce
[    0.000000] Dentry cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
[    0.000000] Inode-cache hash table entries: 4096 (order: 3, 32768 bytes, linear)
[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[    0.000000] Memory: 45904K/63488K available (4455K kernel code, 4160K rwdata, 2048K rodata, 2711K init, 290K bss, 17584K reserved, 0K cma-reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[    0.000000] rcu: Hierarchical RCU implementation.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.
[    0.000000]  Tracing variant of Tasks RCU enabled.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] riscv-intc: 64 local interrupts mapped
[    0.000000] plic: interrupt-controller@c000000: mapped 8 interrupts with 1 handlers for 2 contexts.
[    0.000000] random: get_random_bytes called from start_kernel+0x4d2/0x6c2 with crng_init=0
[    0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0]
[    0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 7052723233920 ns
[    0.000220] sched_clock: 64 bits at 500kHz, resolution 2000ns, wraps every 4398046511000ns
[    0.012014] Timer extension is not available in SBI v0.1
[    0.030320] Console: colour dummy device 128x32
[    0.039670] Calibrating delay loop (skipped), value calculated using timer frequency.. 1.00 BogoMIPS (lpj=5000)
[    0.053426] pid_max: default: 32768 minimum: 301
[    0.085916] LSM: Security Framework initializing
[    0.106152] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear)
[    0.116798] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear)
[    0.463366] cblist_init_generic: Setting adjustable number of callback queues.
[    0.471982] cblist_init_generic: Setting shift to 0 and lim to 1.
[    0.506746] ASID allocator disabled (0 bits)
[    0.543518] rcu: Hierarchical SRCU implementation.
[    0.606262] EFI services will not be available.
[    0.644156] smp: Bringing up secondary CPUs ...
[    0.649526] smp: Brought up 1 node, 1 CPU
[    0.729568] devtmpfs: initialized
[    1.027678] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    1.040342] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
[    1.146192] remote fence extension is not available in SBI v0.1
[    1.176940] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[    2.830826] pps_core: LinuxPPS API ver. 1 registered
[    2.836910] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <[email protected]>
[    2.852106] PTP clock support registered
[    3.008754] clocksource: Switched to clocksource riscv_clocksource
[    4.742462] NET: Registered PF_INET protocol family
[    4.764414] IP idents hash table entries: 2048 (order: 2, 16384 bytes, linear)
[    4.843116] tcp_listen_portaddr_hash hash table entries: 256 (order: 0, 4096 bytes, linear)
[    4.856366] TCP established hash table entries: 512 (order: 0, 4096 bytes, linear)
[    4.867794] TCP bind hash table entries: 512 (order: 1, 8192 bytes, linear)
[    4.878386] TCP: Hash tables configured (established 512 bind 512)
[    4.904076] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
[    4.915416] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
[    4.948946] NET: Registered PF_UNIX/PF_LOCAL protocol family
[    8.140368] workingset: timestamp_bits=46 max_order=14 bucket_order=0
[   11.262946] LiteX SoC Controller driver initialized
[   22.015250] 12003000.serial: ttyLXU0 at MMIO 0x0 (irq = 0, base_baud = 0) is a liteuart
[   22.032188] printk: console [liteuart0] enabled
[   22.032188] printk: console [liteuart0] enabled
[   22.042772] printk: bootconsole [liteuart0] disabled
[   22.042772] printk: bootconsole [liteuart0] disabled
[   23.240688] loop: module loaded
[   25.878566] liteeth 12000800.mac: error -ENXIO: IRQ index 0 not found
[   25.887044] liteeth 12000800.mac: Failed to get IRQ, using polling
[   26.001220] liteeth 12000800.mac eth0: irq 0 slots: tx 2 rx 2 size 2048
[   26.254712] NET: Registered PF_INET6 protocol family
[   26.470926] Segment Routing with IPv6
[   26.480862] In-situ OAM (IOAM) with IPv6
[   26.497858] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[   26.630914] NET: Registered PF_PACKET protocol family
[   26.893754] Warning: unable to open an initial console.
[   26.902926] remote fence extension is not available in SBI v0.1
[   27.446946] Freeing unused kernel image (initmem) memory: 2708K

Unable to boot Linux - userspace cannot write to console, no busybox shell

I'm building LiteX SoC with Rocket on a digilent nexys video board, which is listed as one of the supported platforms here:

./litex-boards/litex_boards/targets/digilent_nexys_video.py --sys-clk-freq 50e6 --with-ethernet --with-sdcard --cpu-type rocket --cpu-variant fulld --csr-json ./newdts.json --build

I have so far built linux with both the litex-rebase, and the master branches on the litex-hub/linux repository. My linux config requires the CONFIG_RISCV_SBI_V01=y option, otherwise it hangs as described here around the loop: module loaded debug message (long before starting init)

With the sbi_v01 option enabled, i manage to get it to boot until the following is seen:

[    0.093898] Run /init as init process
[    0.093923]   with arguments:
[    0.093953]     /init
[    0.093975]   with environment:
[    0.094006]     HOME=/
[    0.094030]     TERM=linux

When using the pre-built initramfs.cpio from the releases here.

I am sure that the init does actually start running, which i tested by creating a custom init executable that segfaults:

#include <stdlib.h>
#include <stdio.h>

#define ERROR(x) { int *tmp = (int*)x; *tmp = 0xDEADBEEF; }

int main() {
    printf("--------------------------- Hello, world!-------------------- \n");
    system("echo \"$$$$$$ HELLO WORLD FROM system()\" >/dev/kmsg");

    ERROR(0xffff0000ffff0000);
}

[    0.093893] Run /init as init process
[    0.093919]   with arguments:
[    0.093948]     /init
[    0.093970]   with environment:
[    0.094002]     HOME=/
[    0.094025]     TERM=linux
[    0.094406] init[1]: unhandled signal 11 code 0x1 at 0xffffff80ffff0000 in init[10000+62000]
[    0.094484] CPU: 0 PID: 1 Comm: init Not tainted 6.3.0-rc3-g640cc8df93a6 #55
[    0.094554] epc : 0000000000010664 ra : 000000000001064a sp : 0000003fcacb7c10
[    0.094627]  gp : 0000000000078bb8 tp : 000000000007e7e0 t0 : 0000000000000002
[    0.094699]  t1 : 0000000000009000 t2 : 000000006fffff41 s0 : 0000003fcacb7c30
[    0.094771]  s1 : 0000000000000001 a0 : 0000000000007f00 a1 : 0000003fcacb78d0
[    0.094843]  a2 : 0000000000000000 a3 : 0000000000000000 a4 : ffffffffdeadbeef
[    0.094915]  a5 : ffff0000ffff0000 a6 : 0000000000074e98 a7 : 0000000000000087
[    0.094987]  s2 : 0000003fcacb7dd8 s3 : 0000000000000001 s4 : 0000003fcacb7de8
[    0.095059]  s5 : 000000000001062a s6 : 0000000000000001 s7 : 0000000000000001
[    0.095131]  s8 : 0000000000000000 s9 : 0000000000000000 s10: 0000000000000000
[    0.095203]  s11: 0000000000000000 t3 : 0000003f836b3000 t4 : 0000000000000011
[    0.095275]  t5 : 0000000000000000 t6 : 0000000000072d80
[    0.095328] status: 8000000200006020 badaddr: ffffff80ffff0000 cause: 000000000000000f
[    0.095412] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
[    0.095484] CPU: 0 PID: 1 Comm: init Not tainted 6.3.0-rc3-g640cc8df93a6 #55
[    0.095554] Call Trace:
[    0.095578] [<ffffffff800051b8>] dump_backtrace+0x1c/0x24
[    0.095632] [<ffffffff804c86bc>] show_stack+0x2c/0x38
[    0.095683] [<ffffffff804d0104>] dump_stack_lvl+0x3c/0x54
[    0.095736] [<ffffffff804d0130>] dump_stack+0x14/0x1c
[    0.095787] [<ffffffff804c87c4>] panic+0xfc/0x284
[    0.095834] [<ffffffff80010b4a>] do_exit+0x704/0x70a
[    0.095883] [<ffffffff80010cbe>] do_group_exit+0x24/0x6c
[    0.095936] [<ffffffff8001ba76>] get_signal+0x7e4/0x814
[    0.095988] [<ffffffff80004486>] do_work_pending+0xfa/0x422
[    0.096044] [<ffffffff800032c2>] resume_userspace_slow+0x8/0xa
[    0.096103] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b ]---

I have tried device trees from both the linux-on-litex-rocket repo, and by making my own using csr_json argument and then json2dts. I have attached the dts i'm currently using to the post.

I have also tried this flow with both linuxd + bbl with rv64imac, and fulld = bbl with rv64imafdc, observing the same issues.

I have additionally tried various permutations of the console= parameter passed to the kernel, but only console=liteuart0 seems to be working correctly, other options such as liteuart, sbi, or ttyLXU0 either result in warning: unable to open initial console errors, or a warning stating that the console argument is malformed during very early stages of the boot.

I have attached the full kernel log too. Thanks

log.txt
mydts.txt

Documentation of the varying rocket cpu-variants

Where can I find information about the different cpu-variants? E.g. linux4, full, linuxd?

Has anyone tried having this fabricated on the OpenMPW shuttle?

Google pays to enable open source hardware to be fabricated for free:

https://developers.google.com/silicon

Has anyone tried having this fabricated on that? If yes, how did it perform?

Add a simplified diagram of the SoC in the README?

Adding a simplified / minimal diagram of the SoC to the README would I think provide a quick and better overview of the aim of the project and what's built with it.

Here is a first attempt I just did:

@gsomlo: If you could be interested, happy to review / do changes to it and create a PR to the README. I also don't want to change the style of the project or transform it, so if you have preference for a full text README or wants to create your own diagram, feel to reject this.

Debug system instabilities

I want to use this project as a basis for running an application with Linux dependencies on Rocket.

First I tried getting https://github.com/tongchen126/Boot-Debian-On-Litex-Rocket project to run. I managed to boot to login and even successfully login a couple of times with both systemd and sysvinit but the majority of times it will just indeterministically hang at random points in or after the boot process (can be in either Kernel/systemd/sysvinit/after login).
Where the hangs after the kernel has started are far more common.
If the hang happens after the Kernel has started then the Kernel will usually still be active (it prints a message if the sdcard gets removed). In that case just the application (bash/systemd/sysvinit/other binaries) seems to become unresponsive.

Second I tried using the /bin/bash shell instead of systemd or sysvinit as they don't seem strictly necessary to run my application.
Here I encounter the same issue. Sometimes my application finishes successfully, sometimes it just randomly hangs (but kernel is still active). Especially on long program runs the probability that the application will hang is very high.

I did run into this issue last year as well when I was using an older version of the system for benchmarking purposes but I didn't have the time investigate this further (so I would just restart until I get a successfull run).

So first of all I was wondering if you @gsomlo encountered instabilities on your Rocket systems.
Second I was wondering if you have any pointers of things that I could look into.
Online I mostly found advice for deterministic hangs in Linux.

For reference I'm using the Arty board and the latest version of Litex.
I already tried different sdcards so I don't think that's an issue.
Additionally I tried using different power supplies.
I'll also try another FPGA when I get my hands on it.
Overall I'm leaning more towards that it's probably a software/gateware issue since BBL and the kernel rarely hang.

hangs and unstable cycle counts

Running some test code. Sometimes the programs (which work perfectly under simulators; including GNU make, a version of the OCaml runtime…) seem to hang (control-C exits though).

Also, when they don't hang, they seem to be randomly affected by some delays leading to high cycle counts.

Could there be that sometimes accesses to the SD card fail and hang programs?

Issue with booting

I have been able to succesfully build the gateware and boot images following the instructions for the nexys4ddr board.
I copy the generated boot.bin, initramfa.cpio, and digilent_nexys4ddr.bit to a USB-stick (also tried SDcard with the same result) but get the following error:

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
             Timeout
Booting from SDCard in SD-Mode...
Booting from boot.json...
Booting from boot.bin...
SDCard boot failed.
Booting from network...
Local IP: 192.168.1.50
Remote IP: 192.168.1.100
Booting from boot.json...
Booting from boot.bin...
Copying boot.bin to 0x80000000...
Network boot failed.
No boot medium found

--============= Console ================--

litex>

How can I debug this? I am suspecting a mismatch between the boot image and the core somehow. I have attached the entire boot sequence from power on.

I have set the jumpers for booting from USB/SD correctly. It worked with another litex system with a 32-bit processor.

boot.log

Simulation (using Verilator) failed

litex/litex/tools/litex_sim.py --threads 4 --opt-level Ofast --cpu-type rocket --cpu-variant linux --with-ethernet [--ram-init boot.bin]

as it is written in the Readme file. Got the following error:

make: Leaving directory '/opt/litex_install/build/sim/software/bios'
INFO:SoC:Initializing ROM rom with contents (Size: 0x6084).
INFO:SoC:Auto-Resizing ROM rom from 0x20000 to 0x6084.
Traceback (most recent call last):
  File "/opt/litex_install/litex/litex/tools/litex_sim.py", line 517, in <module>
    main()
  File "/opt/litex_install/litex/litex/tools/litex_sim.py", line 509, in main
    builder.build(
  File "/opt/litex_install/litex/litex/soc/integration/builder.py", line 367, in build
    vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
  File "/opt/litex_install/litex/litex/soc/integration/soc.py", line 1307, in build
    return self.platform.build(self, *args, **kwargs)
  File "/opt/litex_install/litex/litex/build/sim/platform.py", line 57, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/opt/litex_install/litex/litex/build/sim/verilator.py", line 258, in build
    _compile_sim(build_name, verbose)
  File "/opt/litex_install/litex/litex/build/sim/verilator.py", line 166, in _compile_sim
    raise OSError("Subprocess failed with {}\n{}".format(p.returncode, "\n".join(error_messages)))
OSError: Subprocess failed with 2

Got another error later but it seems to be related to my Verilator 4.110 install (verilator/verilator#2838)

%Error-TIMESCALEMOD: /opt/litex_install/pythondata-cpu-rocket/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.v:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2017 3.14.2.2)
    1 | module IntXbar(
      |        ^~~~~~~
                     /opt/litex_install/build/sim/gateware/sim.v:21:8: ... Location of module with timescale
   21 | module sim (
      |        ^~~

Simulator UART address

Hi, apparently the UART in the simulator is placed at address 0x12003000 instead of 0x12002800 when run with --with-sdram --sdram-init boot.bin, copied from here. I'm not too familiar with the simulator, but there's no main-ram in my simulator, and if I try to add some with --integrated-main-ram-size I get the following error:

{'boot-sim1.bin': '00000000'}
INFO:SoC:        __   _ __      _  __
INFO:SoC:       / /  (_) /____ | |/_/
INFO:SoC:      / /__/ / __/ -_)>  <
INFO:SoC:     /____/_/\__/\__/_/|_|
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2022-09-19 15:40:33)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : SIM.
INFO:SoC:System clock: 1.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Controller ctrl added.
INFO:SoC:CPU rocket added.
INFO:SoC:CPU rocket adding IO Region 0 at 0x12000000 (Size: 0x70000000).
INFO:SoCRegion:Region size rounded internally from 0x70000000 to 0x80000000.
INFO:SoCBusHandler:io0 Region added at Origin: 0x12000000, Size: 0x70000000, Mode: RW, Cached: False Linker: False.
INFO:SoC:CPU rocket overriding rom mapping from 0x00000000 to 0x10000000.
INFO:SoC:CPU rocket overriding sram mapping from 0x01000000 to 0x11000000.
INFO:SoC:CPU rocket overriding main_ram mapping from 0x40000000 to 0x80000000.
INFO:SoC:CPU rocket setting reset address to 0x10000000.
INFO:SoC:CPU rocket adding Bus Master(s).
INFO:SoCBusHandler:cpu_bus0 Bus adapted from Wishbone 64-bit to Wishbone 32-bit.
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoC:CPU rocket adding Interrupt(s).
INFO:SoC:CPU rocket adding DMA Bus.
INFO:SoCDMABusHandler:Creating Bus Handler...
INFO:SoCDMABusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCDMABusHandler:Adding reserved Bus Regions...
INFO:SoCDMABusHandler:Bus Handler created.
INFO:SoCDMABusHandler:dma Region added at Origin: 0x00000000, Size: 0x100000000, Mode: RW, Cached: True Linker: False.
INFO:SoCDMABusHandler:dma added as Bus Slave.
INFO:SoCBusHandler:rom Region added at Origin: 0x10000000, Size: 0x00020000, Mode: RX, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x10000000, Size: 0x00020000, Mode: RX, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x11000000, Size: 0x00002000, Mode: RWX, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x11000000, Size: 0x00002000, Mode: RWX, Cached: True Linker: False.
ERROR:SoCBusHandler:main_ram Region in IO region, it can't be cached: Origin: 0x80000000, Size: 0x00002000, Mode: RWX, Cached: True Linker: False
ERROR:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0                 : Origin: 0x12000000, Size: 0x70000000, Mode: RW, Cached: False Linker: False
Bus Regions: (2)
rom                 : Origin: 0x10000000, Size: 0x00020000, Mode: RX, Cached: True Linker: False
sram                : Origin: 0x11000000, Size: 0x00002000, Mode: RWX, Cached: True Linker: False
Bus Masters: (1)
- cpu_bus0
Bus Slaves: (2)
- rom
- sram

Should the README be updated with the sdram flags (and sim.dts be modified) or am I doing something wrong here?

Here's my whole command line:

litex_sim --threads $(nproc) --with-ethernet --cpu-type rocket --cpu-variant linux --with-sdram --sdram-init boot.bin

toolchains selection issue when building BBL

In the fourth step of this section, the toolchains is configured to use 'riscv64-unknown-linux-gnu'. However, this toolchains is for compiling Linux executable files(i.e., for compiling application on top of Linux with libraries support and not for executing on the bare machine, like bootloader). And the use of this toolchains will trigger errors when compiling bbl.
On the other hand, 'riscv64-unknown-elf' toolchains should be the right choice to compile bbl(for the bare machine), which can be found on this comment by @developandplay.

Encountered error when using 'riscv64-unknown-linux-gnu':

'riscv64-unknown-elf' is fine with this:

Unable to build rocket cpu for terrasic de2 115

Hi,

I am trying litex to generate a rocket based soc for terrasic de2 115.

Command i used to build is:

litex-boards/litex_boards/targets/terasic_de2_115.py --build --cpu-type rocket --cpu-variant linux --sys-clk-freq 50e6

But it generates the following error

Info (12128): Elaborating entity "plusarg_reader" for hierarchy "ExampleRocketSystem:ExampleRocketSystem|SystemBus:subsystem_sbus|TLXbar:system_bus_xbar|TLMonitor:monitor|plusarg_reader:plusarg_reader" File: /home/arun/.local/lib/python3.10/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.v Line: 635
Error (10174): Verilog HDL Unsupported Feature error at plusarg_reader.v(22): system function "$value$plusargs" is not supported for synthesis File: /home/arun/.local/lib/python3.10/site-packages/pythondata_cpu_rocket/verilog/vsrc/plusarg_reader.v Line: 22
Error (12152): Can't elaborate user hierarchy "ExampleRocketSystem:ExampleRocketSystem|SystemBus:subsystem_sbus|TLXbar:system_bus_xbar|TLMonitor:monitor|plusarg_reader:plusarg_reader" File: /home/arun/.local/lib/python3.10/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.v Line: 635
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 329 warnings
    Error: Peak virtual memory: 852 megabytes
    Error: Processing ended: Wed Oct 11 22:46:26 2023
    Error: Elapsed time: 00:00:33
    Error: Total CPU time (on all processors): 00:00:49
Traceback (most recent call last):
  File "/home/arun/litex-boards/litex_boards/targets/terasic_de2_115.py", line 90, in <module>
    main()
  File "/home/arun/litex-boards/litex_boards/targets/terasic_de2_115.py", line 83, in main
    builder.build(**parser.toolchain_argdict)
  File "/home/arun/litex/litex/soc/integration/builder.py", line 367, in build
    vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
  File "/home/arun/litex/litex/soc/integration/soc.py", line 1332, in build
    return self.platform.build(self, *args, **kwargs)
  File "/home/arun/litex/litex/build/altera/platform.py", line 45, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/home/arun/litex/litex/build/generic_toolchain.py", line 123, in build
    self.run_script(script)
  File "/home/arun/litex/litex/build/altera/quartus.py", line 216, in run_script
    raise OSError("Error occured during Quartus's script execution.")
OSError: Error occured during Quartus's script execution.

I am using: Ubuntu 20.04

Quartus:

Quartus Prime Design Software
Version 22.1std.1 Build 917 02/14/2023 SC Lite Edition
Copyright (C) 2023  Intel Corporation. All rights reserved.

Does anyone got a clue on what is wrong? Could it be the quartus version? or something else?

regards
arun

Adjust json2dts.py to work with Rocket

Note: I might be able to pick this up within the next weeks.

just scrolling LEDs

On Nexys-A7, if the MODE jumper is set to JTAG:

Programming the board with openocd -f litex-boards/litex_boards/prog/openocd_xc7_ft2232.cfg -c 'transport select jtag; init; pld load 0 linux-on-litex-rocket/nexys4ddr.bit ; exit' just results in the board scrolling its LEDs without booting anything.

Is there anything else to set?

Resources on creating a proper device tree

Thanks for your help on #7.
Now that I sucessfully flashed the svf (with one warning: Max frequency for clock '$glbnet$main_clkout0': 11.27 MHz (FAIL at 50.00 MHz)) on my board I was following the next steps.
Therefore I was wondering whether you have some more resources on how you created the .dts for your boards.

RocketChip standalone build support is deprecated upstream, requires use of SoC frameworks

Please see the issue here that's raised on the rocketchip's github page:
chipsalliance/rocket-chip#3483

Current upstream RocketChip has moved to using Mill instead of SBT, and the support for building it standalone (like what Litex Rocket update.sh does) is now deprecated and removed due to lack of maintainers.

From one of the contributors: Unfortunately, the standalone rocket-chip build support has been deprecated and removed, due to lack of developer resources to maintain that feature. To build and test SoCs with rocket-chip, users should seek out SoC frameworks., notable options include Chipyard and Playground.

As a result, rebuilding rocket from latest scala sources using update.sh is not possible. I suggest a temporary solution would be to add a checkout for an older commit in update.sh for the time being, at least until some kind of migration path can be adopted.

sqrl_acorn (cle-215+) support

I successfully got a basic thing running with a single core, no FPU, and BBL this morning. Now I'm trying to make a maxed out version with 4 cores, an fpu, and running at 100MHz. I'll post dts and bitstream and other bins here when I get it all working.

zifencei + zicsr needed to build BBL

Building BBL with:

../configure --host=riscv64-unknown-linux-gnu \
             --with-arch=rv64imac \
             --with-payload=../../linux/vmlinux \
             --with-dts=../../conf/nexys4ddr.dts \
             --enable-logo

zicsr and zifence extensions are needed

$ make bbl   
riscv64-unknown-linux-gnu-gcc -MMD -MP -Wall -Werror -D__NO_INLINE__ -mcmodel=medany -O2 -std=gnu99 -Wno-unused -Wno-attributes -fno-delete-null-pointer-checks -fno-PIE  -march=rv64imac -mabi=lp64 -DBBL_LOGO_FILE=\"bbl_logo_file\" -DMEM_START=0x80000000 -fno-stack-protector -U_FORTIFY_SOURCE -DBBL_PAYLOAD=\"bbl_payload\" -DCUSTOM_DTS=\"custom_dts\" -I. -I../pk -I../bbl -I../softfloat -I../dummy_payload -I../machine -I../util -c ../bbl/bbl.c
../bbl/bbl.c: Assembler messages:
../bbl/bbl.c:107: Error: unrecognized opcode `csrr a1,mhartid', extension `zicsr' required

Configured with:

../configure --host=riscv64-unknown-linux-gnu \
             --with-arch=rv64imac_zifencei_zicsr \
             --with-payload=../../linux/vmlinux \
             --with-dts=../../conf/nexys4ddr.dts \
             --enable-logo

Got me the BBL binary compiled.

However, this issue may be a part of rewriting the tutorial as discussed in PR #32

is that possible to generate litex rocket with NVDLA?

Hello,
Chipyard support rocket with NVDLA, but this project only support VCU118. I want to implement this rocket with NVDLA project on other FPGA prototyping paltform. Which means I can't use Xilinx IPcores. So maybe litex open source IPs are good choice. Is that possible to generate litex rocket with NVDLA?

litex_sim fails loading opensbi: Liftoff hangs

Hi, I posted the issue on the main Litex repo (enjoy-digital/litex#1672), but in retrospect heavily believe it to be much more appropriate to have here. I beg of you to review the URL listed above to see what it is I've been getting up to. I am unsure if copy pasting the entire message would be appropriate or not, but would be more than willing to move the entire discussion here if one were to think that I should.

Which cpu architecture to use in BBL building when full rocket (with fp) is used?

I am building the full cpu variant as I have the Kintex 7 device which can hold it, but I do not know which cpu architecture to specify when building BBL. Please advise.

What needs to be done to get Fedora/Debian working on Rocket?

Hello,

I'd like to contribute, and I'm wondering what is currently preventing the RISCV Fedora or Debian ports from working on Rocket. Are there any known issues that prevent it, or does it just fail at some point in the booting process? How recent is the Rocket core being used? Is there anything that needs to be done that I can help with?

build busybox : fatal error:crypt.h No such file

Hi,I I followed the readme to building busybox, but said I was missing this library <crypt.h>, what should I do？